The Research on Software-Hardware Co-designed SEU Fault-Injection Technology
WANG Jing1, RONG Jin-ye2, ZHOU Ji-qin3, YU Hang3, SHEN Jiao3, ZHANG Wei-gong1,3
1. College of Information Engineering, Capital Normal University, Beijing 100048, China;
2. Beijing Microelectronics Technology Institute, Beijing 100076, China;
3. Beijing Key Laboratory of Electronic System Reliability Technology, Capital Normal University, Beijing 100048, China
Abstract：The existing real-world or simulated fault injection methods cannot meet the requirements of reliability verification of nanoscale microprocessors for space applications,since they may introduce problems such as high cost,poor flexibility,poor observability,and low accuracy.This paper proposes a hardware/software cooperated fault injection scheme based on backplane,the time and positions of fault are generated in software,and injected into hardware design at register transfer level.Further,a multi-bit fault model focuses on radiation-induced soft error is proposed for register and memory.Experimental results show that the proposed software and hardware co-designed fault injection platform provides a high automation,randomicity and non-intrusion reliability evaluation method for fault-tolerant processor design.
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2018, Vol. 46 
