电子学报 ›› 2009, Vol. 37 ›› Issue (2): 312-317.

• 论文 • 上一篇    下一篇

一种异构多核处理器的并行流存储结构

邓让钰, 陈海燕, 窦 强, 徐炜遐, 谢伦国, 戴泽福, 李永进, 夏 军, 罗 莉, 张民选   

  1. 国防科学技术大学计算机学院,湖南长沙 410073
  • 收稿日期:2007-07-16 修回日期:2008-08-21 出版日期:2009-02-25 发布日期:2009-02-25

A Parallel Stream Memory Architecture for Heterogeneous Multi-core Processor

DENG Rang-yu, CHEN Hai-yan, DOU Qiang, XU Wei-xia, XIE Lun-guo, DAI Ze-fu, LI Yong-jin, XIA Jun, LUO Li, ZHANG Min-xuan   

  1. School of Computer Science,National University of Defense Technology,Changsha,Hunan 410073,China
  • Received:2007-07-16 Revised:2008-08-21 Online:2009-02-25 Published:2009-02-25

摘要: 异构多核处理器可结合多种处理器体系结构的优势,既保留传统通用体系结构的灵活性,又拥有大量计算资源,可提供更高的峰值计算性能.YHFT64-3异构多核处理器中浮点处理部件18套,峰值计算能力强大,设计与之相匹配的存储系统是一项重大挑战.针对YHFT64-3处理器,本文提出了一种并行流层次存储结构,深入阐述了如何体现应用特点、支持并行数据流处理的存储系统的设计思想和方法,从多个层次实现对并行数据流的挖掘或捕获.测试结果表明,这种存储结构体现了应用特点,能够较好地发挥YHFT64-3处理器的性能,同频情况下(500MHz),YHFT64-3比YHFT64-2性能高2—3个数量级,与1.6GHz的Itanium2性能相当,但代价更低.

关键词: 异构多核处理器, 流体系结构, 预取, 存储调度, 优化的锁步执行模型

Abstract: Heterogeneous multi-core processor can integrate merits of many types of architecture,so it can achieve peak performance as high as processors with special architecture,and keep as flexible as traditional processors at the same time.It is challenging to design a memory sub-system to suit to YHFT64-3,a heterogeneous multi-core processor with 18 float function units.In this paper,a parallel stream memory sub-system architecture is presented for YHFT64-3,its design idea is described,and the principle to find and capture parallel data streams in several levels is detailed.Testing results show that the proposed application-specific memory sub-system can improve system performance significantly.The performance of 500 MHz YHFT64-3 is 2-3 order of that of YHFT64-2 with the same working frequency,and is close to that of 1.6GHz Itanium2 with less cost.

Key words: heterogeneous multi-core processor, stream architecture, prefetch, memory access schedule, OLSM(optimized look-step execution model)

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