电子学报 ›› 2009, Vol. 37 ›› Issue (2): 342-346.

• 论文 • 上一篇    下一篇

基于主方程法单电子晶体管的Verilog-A行为模型

卢 刚, 魏芬芬   

  1. 西安理工大学电子工程系,陕西西安 710048
  • 收稿日期:2007-10-08 修回日期:2008-11-04 出版日期:2009-02-25 发布日期:2009-02-25

A Verilog-A Behavioral Model for SET Based on the Master Equation Method

LU Gang, WEI Fen-fen   

  1. Xi’An University of Technology,Xi’an,Shaanxi 710048,China
  • Received:2007-10-08 Revised:2008-11-04 Online:2009-02-25 Published:2009-02-25

摘要: 基于单电子晶体管的主方程算法,在简化Lientschnig的单电子晶体管模型基础上,建立了基于Verilog-A的单电子晶体管行为描述模型,并利用Cadence Spectre 仿真器对该模型进行了验证.通过单电子晶体管逻辑电路的设计和仿真,表明该模型具有合理的精确度,且速度快,为单电子晶体管电路及混合电路的仿真提供了一种有效的方法.

关键词: 单电子晶体管, 主方程法, Verilog-A, SET逻辑电路

Abstract: Based on the master equation method of single-electron transistor and a simplified Lientschnig’s single-electron transistor (SET) model,this paper presents a Verilog-A behavioral model for SET,and verified by the tool of Cadence Spectre.The model is shown to be reasonably accurate and fast for SET logic circuit simulation.It offers an efficient method for SET circuits and hybrid circuit co-simulation.

Key words: single-electron transistor, master equation method, Verilog-A, SET logic circuit

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