Wrapper Scan Chains Optimization Based on Span and Virtual Layers for Three Dimensional Cores
LIU Jun1,2, WU Xi1,2, PEI Song-wei3, WANG Wei1,2, CHEN Tian1,2
1. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230009, China;
2. Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei, Anhui 230009, China;
3. College of Information Science and Technology, Beijing University of Chemical Technology, Beijing 100029, China
To reduce test time and test cost for pre-bond and post-bond test of three dimensional embedded cores, this paper proposed an optimization method based on span and virtual layers for wrapper scan chains in three dimensional embedded cores.Firstly, the proposed technique made the number of wrapper scan chains in high layers and low layers as equal as possible by maximizing the span of wrapper scan chains.Then, under the constraints of TSVs(Through Silicon Vias)number, the scan elements contained in virtual layers were assigned to wrapper scan chains layer by layer, which effectively balanced the length of pre-bond and post-bond wrapper chains.Experimental results show the presented methodology can greatly reduce the pre-bond/post-bond test time and hardware overhead for three dimensional embedded cores.
刘军, 吴玺, 裴颂伟, 王伟, 陈田. 基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法[J]. 电子学报, 2015, 43(3): 454-459.
LIU Jun, WU Xi, PEI Song-wei, WANG Wei, CHEN Tian. Wrapper Scan Chains Optimization Based on Span and Virtual Layers for Three Dimensional Cores. Chinese Journal of Electronics, 2015, 43(3): 454-459.
[1] AGARWAL V, Hrishikesh M S, KECKLER S W, et al.Clock rate versus IPC:The end of the road for conventional microarchitectures[A].Proceedings of International Symposium on Computer Architecture[C].New York:ACM Press, 2000.248-259.
[2] DAVIS WR, WILSON J, MICK S, et al.Demystifying 3D ICs:The pros and cons of going vertical[J].IEEE Design and Test of Computers, 2005, 22(6):498-510.
[3] BANERJEE K, SOURI S J, KAPUR P, et al.3-D ICs:A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration[J].Proceedings of the IEEE, 2001, 89(5):602-633.
[4] LEE H H S, CHAKRABARTY K.Test challenges for 3D integrated circuits[J].IEEE Design & Test of Computers, 2009, 26(5):26-35.
[5] LEWIS D L, LEE H H S.A scan-island based design enabling pre-bond testability in die-stacked microprocessors[A].Proceedings of International Test Conference[C].Piscataway:IEEE Press, 2007.1-8.
[6] LI J, XIANG D.DfT optimization for pre-bond testing of 3D-SICs containing TSVs[A].Proceedings of International Conference on Computer Design[C].Piscataway:IEEE Press, 2010.474-479.
[7] WU X, FALKENSTERN P, XIE Y.Scan chain design for three-dimensional integrated circuits(3D ICs)[A].Proceedings of International Conference on Computer Design[C].Piscataway:IEEE Press, 2007.208-214.
[8] XIANG D, SHEN K, DENG Y.A thermal-driven test application scheme for 3-dimensional ICs[A].Proceedings of Asian Test Symposium[C].Piscataway:IEEE Press, 2012.101-106.
[9] KIM D H, MUKHOPADHYAY S, LIM S K.Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs[A].Proceedings of International Workshop on System Level Interconnect Prediction[C].New York:ACM Press, 2009.85-92.
[10] PAN D Z, LIM S K, ATHIKULWONGSE K, et al.Design for manufacturability and reliability for TSV-based 3D ICs[A].Proceedings of Asia and South Pacific Design Automation Conference[C].Piscataway:IEEE Press, 2012.750-755.
[11] HSIEH A C, HWANG T, CHANG M T, et al.TSV redundancy:Architecture and design issues in 3D IC[A].Proceedings of Design, Automation, and Test in Europe[C].Piscataway:IEEE Press, 2010.166-171.
[12] NOIA B, CHAKRABARTY K, XIE Y.Test-wrapper optimization for embedded cores in TSV-based three-dimensional SoC[A].Proceedings of International Conference on Computer Design[C].Piscataway:IEEE Press, 2009.70-77.
[13] CHENGY, ZHANG L, HAN Y, et al.Wrapper chain design for testing tsvs minimization in circuit-partitioned 3D SoC[A].Proceedings of Asian Test Symposium[C].Piscataway:IEEE Press, 2011.181-186.
[14] LEWIS D L, PANTH S, ZHAO X, et al.Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores[A].Proceedings of International Conference on Computer Design[C].Piscataway:IEEE Press, 2011.90-95.
[15] IYENGAR V, CHAKRABARTY K, MARINISSEN E J.Test wrapper and test access mechanism co-optimization for system-on-a-chip[J].Journal of Electronic Testing:Theory and Applications, 2002, 18(2):213-230.
[16] 邓立宝, 乔立岩, 俞洋, 彭喜元.基于差值二次分配的扫描链平衡算法[J].电子学报, 2012, 40(2):338-343. DENG Li-bao, QIAO Li-yan, YU Yang, PENG Xi-yuan.Wrapper scan chains balance algorithm base on twice-assigned method by the chains difference[J].Acta Electronica Sinica, 2012, 40(2):338-343.(in Chinese)