Pareto Dominance Based Area and Reliability Optimization of MPRM Circuits
BU Deng-li1,2,3, JIANG Jian-hui2
1. School of Electronics and Information Engineering, Jinggangshan University, Ji'an, Jiangxi 343009, China;
2. School of Software Engineering, Tongji University, Shanghai 201804, China;
3. Key Laboratory of Watershed Ecology and Geographical Environment Monitoring NASG, Ji'an, Jiangxi 343009, China
Area and SER (Soft Error Rate) evaluation models at logic level are proposed for area and reliability optimization of MPRM (Mixed-Polarity Reed-Muller) circuits,the trade-off between area and reliability is achieved by using Pareto dominance based multiobjective optimization.The area is computed by decomposing the XOR part of MPRM circuit as trees of XOR gates and counting in XOR gate sharing among multiple outputs.The SER is computed by using signal probability and fault propagation techniques,and taking into account the logic masking effects and correlations among signals in the circuit network.Based on the proposed area and SER evaluation models,the Pareto optimal set for area and SER of MPRM circuit is obtained by using polarity optimization method with Gray code based exhaustive search strategy,the final solution is selected by using a metric called efficiency factor.Experimental results by using a set of benchmark circuits from MCNC show that,in comparison with the MPRM circuits with minimized area,the selected MPRM circuits have improved reliability with less area overhead.
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2016, Vol. 44 
