摘要 Amdahl's law is a simple and fundamental tool for understanding the evolution of performance as a function of parallelism. Following a recent trend on timing and power analysis of general purpose many-core chip using this law, we develop a novel PIP Panalytical model for evaluating the performance and power of hierarchical on-chip large-scale parallel architectures with the core number, super-node size, processing element number, and function unit number taken into consideration. We thereby investigate the influence of workload characteristics (Thread-level parallel TLP, Instruction-level parallel IL Pand Data-level parallel DLP) on resource allocation with the restriction of performance and power. The results provide some feasible options to design TOPS level DS Parchitecture as well as a theoretical basis for making the design more scalable.
Abstract：Amdahl's law is a simple and fundamental tool for understanding the evolution of performance as a function of parallelism. Following a recent trend on timing and power analysis of general purpose many-core chip using this law, we develop a novel PIP Panalytical model for evaluating the performance and power of hierarchical on-chip large-scale parallel architectures with the core number, super-node size, processing element number, and function unit number taken into consideration. We thereby investigate the influence of workload characteristics (Thread-level parallel TLP, Instruction-level parallel IL Pand Data-level parallel DLP) on resource allocation with the restriction of performance and power. The results provide some feasible options to design TOPS level DS Parchitecture as well as a theoretical basis for making the design more scalable.
This work is supported by the National Natural Science Foundation of China (No.61070036, No.61133007).
通讯作者:
YANG Hui, CHEN Shuming
E-mail: huihui19870124@126.com;smchen@nudt.edu.cn
作者简介: WU Tiebin was born in 1987. He received the B.E. and M.E. degrees from the School of Computer Science, National University of Defense Technology (NUDT), Changsha, China, in 2009 and 2011, respectively. Her research interests include modeling and simulation of DS Psystem and micro-architecture.
引用本文:
YANG Hui, CHEN Shuming, WU Tiebin. Parameterized Integrated Power and Performance (PIPP) Model for Ultra High-Performance of TOPS level DSP[J]. 电子学报, 2013, 22(4): 707-711.
YANG Hui, CHEN Shuming, WU Tiebin. Parameterized Integrated Power and Performance (PIPP) Model for Ultra High-Performance of TOPS level DSP. Chinese Journal of Electronics, 2013, 22(4): 707-711.
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