Design of a Self-Biased Low-Jitter Low-Power Phase-Locked Loop for SerDes

SUN Xinzhuo; LIN Changlong; DING Jianping; ZHAO Yiqiang; LI Yao

doi:10.12263/DZXB.20250707

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Design of a Self-Biased Low-Jitter Low-Power Phase-Locked Loop for SerDes

PAPERS | 更新时间：2026-07-30

- Design of a Self-Biased Low-Jitter Low-Power Phase-Locked Loop for SerDes
- ACTA ELECTRONICA SINICA Vol. 54, Issue 4, Pages: 1872-1884(2026)
- 作者机构：
  
  1.天津大学微电子学院，天津 300072
  2.龙芯中科技术股份有限公司芯片研发部，北京 100080
  3.中国科学技术大学微电子学院，安徽合肥 230026
- 作者简介：
- 基金信息：
  
  Natural Science Foundation of Tianjin(24JCQNJC1370)
- DOI：10.12263/DZXB.20250707
  CLC： TN492;TN911.8
- Received：14 August 2025，
  
  Accepted：01 April 2026，
  
  Online First：12 May 2026，
  
  Published：25 April 2026
- 稿件说明：
移动端阅览
孙欣茁, 林长龙, 丁健平, 等. 一种基于自偏置技术的低功耗低抖动SerDes时钟源锁相环设计[J]. 电子学报, 2026, 54(04): 1872-1884.

SUN Xinzhuo, LIN Changlong, DING Jianping, et al. Design of a Self-Biased Low-Jitter Low-Power Phase-Locked Loop for SerDes[J]. Acta Electronica Sinica, 2026, 54(04): 1872-1884.
孙欣茁, 林长龙, 丁健平, 等. 一种基于自偏置技术的低功耗低抖动SerDes时钟源锁相环设计[J]. 电子学报, 2026, 54(04): 1872-1884. DOI：10.12263/DZXB.20250707

SUN Xinzhuo, LIN Changlong, DING Jianping, et al. Design of a Self-Biased Low-Jitter Low-Power Phase-Locked Loop for SerDes[J]. Acta Electronica Sinica, 2026, 54(04): 1872-1884. DOI：10.12263/DZXB.20250707

摘要

相比于传统二阶锁相环（Phase-Locked Loop，PLL)结构，自偏置锁相环可在宽动态范围内保持环路稳定性和响应速度不变，具有很高的频率稳定性，可满足各种高精度频率控制应用需求，适合作为满足多协议标准的串行器/解串器（Serializer/Deserializer，SerDes）物理层（PHysical Layer，PHY）电路时钟源使用，在宽频率范围和一定电压范围内具有稳定环路特性。传统自偏置锁相环使用两个电荷泵产生对称辅助电压

fs1

和

fs2

，这会增加系统功耗和面积，并且版图失配

会在

fs1

和

fs2

之间引入静态失配，电路工作过程中电源压降和局部噪声会在

fs1

和

fs2

之间引入动态失配，这些失配会增加压控振荡器的相位噪声和时钟抖动。针对这一问题，本文设计了一款低功耗低失配电荷泵结构，由一个电荷泵电路产生

fs1

和

fs2

，该结构通过共用电流偏置部分降低系统功耗，通过设计改进减小输出失配。在实际工作中本设计可同时满足外围组件快速互连（Peripheral Component Interconnect express，PCIe）1.0/2.0/3.0、通用串行总线（Universal Serial Bus，USB）3.0、串行高级技术附件（Serial Advanced Technology Attachment，SATA）1/2/3物理层协议的时钟源要求。SerDes中每4个数据单元共用1个时钟单元，4个数据单元可分别配置成PCIe的任何速率或分别配置成USB及SATA的任何速率。全电路工作在0.9 V低电压下，锁相环面积为0.055 3 mm

，压控振荡器（Voltage-Controlled Oscillator，VCO）的调谐范围是3~5 GHz，环路分频采用6~511分频，输出分频采用1~255分频，输出频率范围是11.76 MHz~5 GHz。后仿真结果表明，锁相环锁定时间2 μs，相位噪声为-110 dBc/Hz@1 MHz，功耗为5.54 mW。测试结果表明，-40~125 ℃范围内2 000片PLL测试成品率大于99%；经过片上长距离传输并通过SerDes发送端所送出高速时钟的抖动测试结果远大于仿真结果，测试结果为2.5 GHz时钟：Random jitter 2.41 ps、period jitter 10.8 ps；4 GHz时钟：Random jitter 1.8 ps、period jitter 9.28 ps。上述高速时钟经过复杂通路送出导致jitter较大，而PCIe插槽上100 MHz参考时钟也由PLL产生，其到输出PAD的路径很短，测试路径引入的抖动较少可直接测试，采用示波器内嵌PCIe参考时钟测试软件对PCIe插槽上参考时钟进行测试，RMS jitter（Root-Mean-Square jitter）最差为0.776 8 ps。为证明本文提出的PLL抖动性能满足SerDes PHY，进行PCIe PHY GEN2速率和GEN3速率测试，所有结果均满足协议要求且Margin很大。

Abstract

Compared with conventional second-order PLL (Phase-Locked Loop)

the self-biased PLL stands out with its remarkable capability to maintain consistent loop stability and response speed across an extensive dynamic range

while also delivering superior frequency stability. These inherent advantages enable it to satisfy the demanding requirements of various high-precision frequency control applications

rendering it an ideal candidate for serving as the clock source of SerDes (Serializer/Deserializer) PHY (Physical Layer) circuits that are compliant with multiple protocol standards. What is more

the self-biased PLL can provide stable loop characteristics not only over a broad frequency range but also within a specific voltage range

which further exp

ands its applicability in complex electronic systems. In traditional self-biased PLL architectures

two separate charge pumps are typically utilized to generate symmetric auxiliary voltages

namely

fs1

and

fs2

. However

this dual-charge-pump configuration inevitably leads to increased system power consumption and a larger chip area footprint

which are critical drawbacks in modern high-density

low-power integrated circuit designs. Additionally

layout mismatches during the manufacturing process can introduce static offsets between

fs1

and

fs2

. To make matters worse

power supply voltage drops and local noise interference that occur during circuit operation will give rise to dynamic mismatches between these two auxiliary voltages. Both static and dynamic mismatches can significantly degrade the performance of the VCO (Voltage-Controlled Oscillator )

manifesting as increased phase noise and clock jitter

which are detrimental to the overall signal integrity of the SerDes PHY system. To tackle the aforementioned issues comprehensively

this paper presents a novel low-power

low-mismatch charge pump structure that is capable of generating both

fs1

and

fs2

using a single charge pump circuit. The core innovation of this design lies in the sharing of the current bias section among the two output voltage branches

which effectively reduces the number of active components and thus cuts down the overall system power consumption substantially. Furthermore

targeted design improvements

such as symmetric circuit layout optimization and precision current mirror calibration

are implemented to minimize the output mismatches between

fs1

and

fs2

thereby mitigating the adverse impacts of static and dynamic offsets on the VCO performance. In practical operation scenarios

the proposed self-biased PL

L design can simultaneously act as the clock source for SerDes PHY circuits adhering to a diverse set of mainstream protocols

including PCIe (Peripheral Component Interconnect express) 1.0/2.0/3.0

USB (Universal Serial Bus) 3.0

and SATA (Serial Advanced Technology Attachment) 1/2/3. A key feature of its application in SerDes systems is that every four data units share one dedicated clock unit

and each of these four data units can be independently configured to operate at any data rate specified by the PCIe protocol

or alternatively

be set to run at any rate supported by the USB and SATA protocols respectively. This high degree of configurability makes the PLL highly adaptable to the heterogeneous communication requirements of modern electronic devices. The full integrated circuit of the proposed PLL operates at a low supply voltage of 0.9 V

which is conducive to low-power operation in battery-powered devices. The chip area occupied by the PLL core is merely 0.055 3 mm²

demonstrating excellent area efficiency that is essential for integration into compact SerDes PHY chips. The PLL achieves a wide frequency tuning range spanning from 3 GHz to 5 GHz for VCO

covering the frequency bands required by most of the targeted protocols. The loop divider supports division ratios from 6 to 511

and the output divider supports ratios from 1 to 255

resulting in an output frequency range of 11.76 MHz to 5 GHz. Post-layout simulation results validate the superior performance of the design: the PLL exhibits a fast locking time of 2 μs

a low phase noise of -110 dBc/Hz at an offset frequency of 1 MHz

and a total power consumption of only 5.54 mW

all of which outperform many conventional self-biased PLL designs. Experimental test results further confirm the robustness and reliability of the proposed PLL. Specifically

the yield rate of 2 000 fabricated PLL chips exceeds 99% when operating within the extreme temperature range from -40 °C to 125 °C

indicating excellent manufacturing compatibility and environmental adaptab

ility. Moreover

the jitter test results of the high-speed clock signals transmitted on-chip and output by the SerDes transmitter are significantly larger than the simulation predictions. At an operating frequency of 2.5 GHz

the measured RJ (Random Jitter) is 2.41 ps and the PJ (Period Jitter) is 10.8 ps; when the frequency is increased to 4 GHz

the random jitter is reduced to 1.8 ps and the period jitter is 9.28 ps. The aforementioned high-speed clock incurs significant jitter due to transmission through a complex path. In contrast

the 100 MHz reference clock for the PCIe slot generated by the PLL features an extremely short transmission path to the output PAD

the jitter introduced by the test path is minimal and can be directly measured. A dedicated PCIe reference clock test software embedded in the oscilloscope was adopted to characterize the reference clock at the PCIe slot

with the worst-case RMS (Root-Mean-Square) jitter measured at 0.776 8 ps. To verify the suitability of the proposed PLL structure for SerDes PHY applications

rigorous compliance tests were conducted at PCIe PHY Gen2 and Gen3 data rates. All test metrics not only meet the stringent requirements specified in the corresponding protocol standards but also exhibit ample margins

which provide a solid guarantee for the stable operation of the SerDes system in real-world applications.

关键词

Keywords

references

曾兆权 , 旭阳欣 , 马丁·马林森 , 等 . 一种基于有限脉冲响应滤波器的时钟倍频器设计 [J ] . 电子学报 , 2023 , 51 ( 10 ): 2791 - 2800 . DOI: 10.12263/DZXB.20220932 http://dx.doi.org/10.12263/DZXB.20220932

Zeng Zhaoquan , Xu Yangxin , Mallinson M , et al . A design of clock frequency multiplication circuit based on finite impulse response filter [J ] . Acta Electronica Sinica , 2023 , 51 ( 10 ): 2791 - 2800 . (in Chinese) . DOI: 10.12263/DZXB.20220932 http://dx.doi.org/10.12263/DZXB.20220932

桑浩 , 袁珩洲 , 郭阳 , 等 . 一种用于片上时钟系统的单粒子不敏感振荡器 [J ] . 电子学报 , 2025 , 53 ( 9 ): 3202 - 3210 .

Sang Hao , Yuan Hengzhou , Guo Yang , et al . A single-event immune oscillator for on-chip clock systems [J ] . Acta Electronica Sinica , 2025 , 53 ( 9 ): 3202 - 3210 . (in Chinese)

周高磊 , 毛陆虹 , 谢生 , 等 . 高速率、高摆幅的CMOS光接收机模拟前端电路设计 [J ] . 天津大学学报(自然科学与工程技术版) , 2021 , 54 ( 11 ): 1187 - 1193 . DOI: 10.11784/tdxbz202008002 http://dx.doi.org/10.11784/tdxbz202008002

Zhou Gaolei , Mao Luhong , Xie Sheng , et al . Design of high-speed, high-swing analog front-end circuit in CMOS [J ] . Journal of Tianjin University (Science and Technology) , 2021 , 54 ( 11 ): 1187 - 1193 . (in Chinese) . DOI: 10.11784/tdxbz202008002 http://dx.doi.org/10.11784/tdxbz202008002

文溢 , 陈建军 , 梁斌 , 等 . 28 nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究 [J ] . 电子学报 , 2022 , 50 ( 11 ): 2653 - 2658 . DOI: 10.12263/DZXB.20211691 http://dx.doi.org/10.12263/DZXB.20211691

Wen Yi , Chen Jianjun , Liang Bin , et al . Research on single-event radiation characteristics of an 8-Gbps SerDes in a 28 nm CMOS technology [J ] . Acta Electronica Sinica , 2022 , 50 ( 11 ): 2653 - 2658 . (in Chinese) . DOI: 10.12263/DZXB.20211691 http://dx.doi.org/10.12263/DZXB.20211691

Yuan Hengzhou , Guo Yang , Liu Yao , et al . A self-biased low-jitter process-insensitive phase-locked loop for 1.25 Gb/s-6.25 Gb/s SerDes [J ] . Chinese Journal of Electronics , 2018 , 27 ( 5 ): 1009 - 1014 . DOI: 10.1049/cje.2018.02.003 http://dx.doi.org/10.1049/cje.2018.02.003

Ghosh P P , Xiao E . A 2.5 GHz radiation hard fully self-biased PLL using 0.25 µm SOS-CMOS technology [C ] // 2009 IEEE International Conference on IC Design and Technology . Piscataway : IEEE , 2009 : 121 - 124 . DOI: 10.1109/ICICDT.2009.5166278 http://dx.doi.org/10.1109/ICICDT.2009.5166278 .

Xu Dingxin , Zhang Yuncheng , Huang Hongye , et al . A 6.5-to-8-GHz cascaded dual-fractional- N digital PLL achieving -52.79-dBc fractional spur with 50-MHz reference [J ] . IEEE Journal of Solid-State Circuits , 2025 , 60 ( 3 ): 1043 - 1055 . DOI: 10.1109/JSSC.2024.3447021 http://dx.doi.org/10.1109/JSSC.2024.3447021 .

Duan Yu , Zhu Yan , Martins R P , et al . A PVT-robust 5.5 GHz fractional-N cascaded RO-based digital PLL with voltage-domain feedforward noise cancellation [C ] // 2025 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2025 : 324 - 326 . DOI: 10.1109/ISSCC49661.2025.10904636 http://dx.doi.org/10.1109/ISSCC49661.2025.10904636 .

林美东 , 文治平 , 张健 . 基于自偏置技术的高速SERDES芯片PLL设计 [J ] . 微处理机 , 2016 , 37 ( 3 ): 1 - 4 . DOI: 10.3969/j.issn.1002-2279.2016.03.001 http://dx.doi.org/10.3969/j.issn.1002-2279.2016.03.001

Lin Meidong , Wen Zhiping , Zhang Jian . PLL design of high speed SERDES chips based on self-biased technique [J ] . Microprocessors , 2016 , 37 ( 3 ): 1 - 4 . (in Chinese) . DOI: 10.3969/j.issn.1002-2279.2016.03.001 http://dx.doi.org/10.3969/j.issn.1002-2279.2016.03.001

Maneatis J G . Low-jitter process-independent DLL and PLL based on self-biased techniques [J ] . IEEE Journal of Solid-State Circuits , 1996 , 31 ( 11 ): 1723 - 1732 . DOI: 10.1109/JSSC.1996.542317 http://dx.doi.org/10.1109/JSSC.1996.542317 .

Maneatis J G , Kim J , McClatchie I , et al . Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL [J ] . IEEE Journal of Solid-State Circuits , 2003 , 38 ( 11 ): 1795 - 1803 . DOI: 10.1109/JSSC.2003.818298 http://dx.doi.org/10.1109/JSSC.2003.818298 .

Hu Ang , Liu Dongsheng , Zhang Kefeng . A 0.03- to 3.6-GHz frequency synthesizer with self-biased VCO and quadrature-input quadrature-output frequency divider [J ] . IEEE Transactions on Circuits and Systems II: Express Briefs , 2019 , 66 ( 12 ): 1997 - 2001 . DOI: 10.1109/TCSII.2019.2899506 http://dx.doi.org/10.1109/TCSII.2019.2899506 .

Liu Yajiao , Yue Suge , Han Xupeng , et al . A low-jitter 10GHz PLL based on adaptive bandwidth technique for muti-rate serial link data transmitter [C ] // 2019 IEEE 3rd Information Technology, Networking, Electronic and Automation Control Conference (ITNEC) . Piscataway : IEEE , 2019 : 2209 - 2212 . DOI: 10.1109/ITNEC.2019.8729505 http://dx.doi.org/10.1109/ITNEC.2019.8729505 .

Zhong Naizao , Zhang Runxi , Shi Chunqi , et al . A bandwidth-tracking self-biased 5-to-2800 MHz low-jitter clock generator in 55nm CMOS [C ] // 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) . Piscataway : IEEE , 2018 : 57 - 60 . DOI: 10.1109/APCCAS.2018.8605563 http://dx.doi.org/10.1109/APCCAS.2018.8605563 .

Wang Binghui , Yang Haigang , Jia Yiping . A 3-6 GHz 5-to-512 multiplier adaptive fast-locking self-biased PLL in 28nm CMOS [C ] // 2021 IEEE International Symposium on Circuits and Systems (ISCAS) . Piscataway : IEEE , 2021 : 1 - 5 . DOI: 10.1109/ISCAS51556.2021.9401165 http://dx.doi.org/10.1109/ISCAS51556.2021.9401165 .

邓涵 , 韦雪明 , 尹仁川 , 等 . 一种自适应可重构宽带低抖动锁相环时钟 [J ] . 微电子学 , 2023 , 53 ( 1 ): 89 - 94 . DOI: 10.13911/j.cnki.1004-3365.220056 http://dx.doi.org/10.13911/j.cnki.1004-3365.220056 .

Deng Han , Wei Xueming , Yin Renchuan , et al . A wideband low jitter PLL clock with adaptive reconfigurable charge pump [J ] . Microelectronics , 2023 , 53 ( 1 ): 89 - 94 . DOI: 10.13911/j.cnki.1004-3365.220056. http://dx.doi.org/10.13911/j.cnki.1004-3365.220056. (in Chinese)

Viswanathan B , Nair S R R , Viswam V , et al . 4 GHz 130nm low voltage PLL based on self biased technique [C ] // 2010 23rd International Conference on VLSI Design . Piscataway : IEEE , 2010 : 330 - 334 . DOI: 10.1109/VLSI.Design.2010.21 http://dx.doi.org/10.1109/VLSI.Design.2010.21 .

盛炜 , 张国华 , 杨霄垒 , 等 . 一种基于自偏置技术的低抖动锁相环 [J ] . 微电子学 , 2017 , 47 ( 3 ): 351 - 354 . DOI: 10.13911/j.cnki.1004-3365.2017.03.013 http://dx.doi.org/10.13911/j.cnki.1004-3365.2017.03.013 .

Sheng Wei , Zhang Guohua , Yang Xiaolei , et al . A low jitter PLL based on self－biased technique [J ] . Microelectronics , 2017 , 47 ( 3 ): 351 - 354 . DOI: 10.13911/j.cnki.1004-3365.2017.03.013. http://dx.doi.org/10.13911/j.cnki.1004-3365.2017.03.013. (in Chinese)

王子轩 , 王山虎 , 王鑫 , 等 . 一种基于相位误差校正技术的快速启动晶体振荡器 [J ] . 电子学报 , 2024 , 52 ( 4 ): 1182 - 1188 .

Wang Zixuan , Wang Shanhu , Wang Xin , et al . A fast startup crystal oscillator based on phase-error correction technique [J ] . Acta Electronica Sinica , 2024 , 52 ( 4 ): 1182 - 1188 . (in Chinese)

陈喆 , 王品清 , 周培根 , 等 . 基于45 nm CMOS SOI工艺的毫米波双频段低相噪压控振荡器设计 [J ] . 电子学报 , 2024 , 52 ( 7 ): 2161 - 2169 . DOI: 10.12263/DZXB.20230645 http://dx.doi.org/10.12263/DZXB.20230645

Chen Zhe , Wang Pinqing , Zhou Peigen , et al . Design of a millimeter-wave dual-band low phase noise VCO in 45 nm CMOS SOI process [J ] . Acta Electronica Sinica , 2024 , 52 ( 7 ): 2161 - 2169 . (in Chinese) . DOI: 10.12263/DZXB.20230645 http://dx.doi.org/10.12263/DZXB.20230645

范昊 , 黄鲁 , 胡腾飞 . 一种基于自偏置技术的低功耗锁相环设计 [J ] . 微电子学 , 2015 , 45 ( 2 ): 196 - 199 . DOI: 10.13911/j.cnki.1004-3365.2015.02.012 http://dx.doi.org/10.13911/j.cnki.1004-3365.2015.02.012 .

Fan Hao , Huang Lu , Hu Tengfei . Design of a low power PLL based on self-biased techniques [J ] . Microelectronics , 2015 , 45 ( 2 ): 196 - 199 . DOI: 10.13911/j.cnki.1004-3365.2015.02.012. http://dx.doi.org/10.13911/j.cnki.1004-3365.2015.02.012. (in Chinese)

赵毅强 , 叶泽宇 , 叶茂 , 等 . 具有快速再锁定特性的亚采样锁相环设计 [J ] . 天津大学学报(自然科学与工程技术版) , 2024 , 57 ( 7 ): 711 - 720 .

Zhao Yiqiang , Ye Zeyu , Ye Mao , et al . Design of a sub-sampling phase-locked loop with fast relocking characteristics [J ] . Journal of Tianjin University (Science and Technology) , 2024 , 57 ( 7 ): 711 - 720 . (in Chinese)

Trivedi P , Tiwari B B . High operating frequency, low-power PFD for PLL applications [C ] // 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT) . Piscataway : IEEE , 2023 : 1 - 5 . DOI: 10.1109/ICCCNT56998.2023.10307191 http://dx.doi.org/10.1109/ICCCNT56998.2023.10307191 .

傅海鹏 , 毕宇昕 , 王志鹏 , 等 . 0.15～5.8 GHz超宽带多功能锁相环设计 [J ] . 湖南大学学报(自然科学版) , 2025 , 52 ( 6 ): 187 - 194 . DOI: 10.16339/j.cnki.hdxbzkb.2025188 http://dx.doi.org/10.16339/j.cnki.hdxbzkb.2025188 .

Fu Haipeng , Bi Yuxin , Wang Zhipeng , et al . Design of multifunctional phase-locked loop for 0.15~5.8 GHz ultra wideband [J ] . Journal of Hunan University (Natural Sciences) , 2025 , 52 ( 6 ): 187 - 194 . DOI: 10.16339/j.cnki.hdxbzkb.2025188. http://dx.doi.org/10.16339/j.cnki.hdxbzkb.2025188. (in Chinese)

李铁虎 , 郭超东 , 张伟 , 等 . 一种基于65 nm CMOS工艺的低相噪低功耗电荷泵锁相环 [J ] . 微电子学 , 2025 , 55 ( 3 ): 364 - 369 . DOI: 10.13911/j.cnki.1004-3365.240204 http://dx.doi.org/10.13911/j.cnki.1004-3365.240204 .

Li Tiehu , Guo Chaodong , Zhang Wei , et al . A low phase noise low power CPPLL based on 65 nm CMOS process [J ] . Microelectronics , 2025 , 55 ( 3 ): 364 - 369 . DOI: 10.13911/j.cnki.1004-3365.240204. http://dx.doi.org/10.13911/j.cnki.1004-3365.240204. (in Chinese)

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