A Broadband High-Linearity CMOS Low-Noise Amplifier for K/Ka-Band Applications

LUO Jiang; LUO Jun; ZENG Xinxi

doi:10.12263/DZXB.20260421

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A Broadband High-Linearity CMOS Low-Noise Amplifier for K/Ka-Band Applications

RF Computing | 更新时间：2026-10-16

- A Broadband High-Linearity CMOS Low-Noise Amplifier for K/Ka-Band Applications
- ACTA ELECTRONICA SINICA Vol. 54, Issue 6, Pages: 2470-2480(2026)
- 作者机构：
  
  1.杭州电子科技大学电子信息学院，浙江杭州 310018
  2.北京科技大学机械工程学院，北京 100083
  3.东南大学毫米波全国重点实验室，江苏南京 210096
- 作者简介：
- 基金信息：
  
  National Key Research and Development Program of China(2023YFB3811503);National Natural Science Foundation of China(52302132);The State Key Laboratory of Millimeter Waves(KN202501-01)
- DOI：10.12263/DZXB.20260421
  CLC： TN402;TN722.3
- Received：31 March 2026，
  
  Accepted：27 April 2026，
  
  Published：25 June 2026
- 稿件说明：
移动端阅览
罗将, 罗军, 曾新喜. 面向K/Ka波段应用的宽带高线性CMOS低噪声放大器设计[J]. 电子学报, 2026, 54(06): 2470-2480.

LUO Jiang, LUO Jun, ZENG Xinxi. A Broadband High-Linearity CMOS Low-Noise Amplifier for K/Ka-Band Applications[J]. Acta Electronica Sinica, 2026, 54(06): 2470-2480.
罗将, 罗军, 曾新喜. 面向K/Ka波段应用的宽带高线性CMOS低噪声放大器设计[J]. 电子学报, 2026, 54(06): 2470-2480. DOI：10.12263/DZXB.20260421

LUO Jiang, LUO Jun, ZENG Xinxi. A Broadband High-Linearity CMOS Low-Noise Amplifier for K/Ka-Band Applications[J]. Acta Electronica Sinica, 2026, 54(06): 2470-2480. DOI：10.12263/DZXB.20260421

摘要

在毫米波通信技术快速发展的背景下，面向高质量、大容量数据传输的射频前端电路需求不断提升。作为接收机前端的关键模块，低噪声放大器（Low-Noise Amplifier，LNA）不仅需要具备低噪声系数（Noise Figure，NF）以提高系统对微弱信号的检测灵敏度，还需保持较高线性度，以应对强干扰和复杂调制信号环境下的增益压缩与信号失真问题。特别是在宽带工作条件下，如何在低噪声、高增益和高线性度之间实现有效平衡，仍是毫米波集成电路设计中的重要挑战。针对上述需求，本文基于55 nm互补金属氧化物半导体（Complementary Metal-Oxide-Semiconductor，CMOS）工艺，设计并实现了一款面向K/Ka波段的高

线性度宽带低噪声放大器芯片。电路采用两级共源共栅（Cascode）拓扑结构，并在跨导管源极引入电感退化反馈，以拓展输入电压摆幅并改善大信号线性度。同时，本文定量分析了偏置条件对晶体管三阶非线性跨导项的影响，将主放大晶体管偏置在三阶跨导

零点附近，从而有效抑制非线性失真并提升输入1 dB压缩点（Input 1 dB compression Point，IP

1 dB

）。此外，利用栅极电容峰化策略对高频增益响应进行补偿，进一步改善了宽带范围内的增益性能。在版图设计方面，本文采用三维交错布局策略，通过优化晶体管指状结构及金属层间空间排布，降低毫米波频段下敏感的栅极寄生电阻和源极寄生电感，减小关键互连寄生效应对噪声、增益和稳定性的影响，从而提升电路在高频宽带条件下的综合性能。测试结果表明，所提出LNA在21.5~30.3 GHz频段内实现了16.8 dB的峰值增益、8.8 GHz的3 dB带宽和3.26 dB的最低噪声系数；实测IP

1 dB

最高可达

https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=120459907&type=

https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=120459906&type=

1.69333339

2.28600001

3.6 dBm，核心面积仅为0.11 mm²。上述结果验证了所提方法在提升毫米波LNA综合性能方面的有效性，可为高动态范围毫米波接收前端中的LNA设计提供一种有潜力的技术方案。

Abstract

With the rapid development of millimeter-wave communication systems

radio-frequency front-end circuits are increasingly required to support high-quality and high-capacity data transmission. As a key building block in the receiver front-end

the low-noise amplifier (LNA) must provide a low noise figure (NF) for high sensitivity while maintaining sufficient linearity to alleviate gain compression and signal distortion under strong interferers and complex modulation scenarios. However

achieving low noise

high gain

and high linearity simultaneously over a wide bandwidth remains challenging for millimeter-wave integrated circuit design. To address these challenges

this paper presents a K/Ka-band high-linearity wideband LNA implemented in a 55 nm complementary metal-oxide-semiconductor (CMOS) process. The proposed LNA adopts a two-stage cascode topology

in which source inductive degeneratio

n is introduced in the common-source transistors to extend the input voltage swing and improve large-signal linearity. The bias-dependent third-order transconductance nonlinearity is quantitatively analyzed

and the main amplifying transistors are biased near the zero-crossing point of

thereby suppressing third-order nonlinear distortion and improving the input 1 dB compression point (IP

1 dB

). In addition

a gate-capacitance peaking strategy is employed to compensate the high-frequency gain response

further improving the gain performance over a broad bandwidth. A three-dimensional interdigitated layout strategy is further developed to optimize the transistor finger structure and metal-layer arrangement. This approach reduces the parasitic gate resistance and source inductance

which are particularly detrimental at millimeter-wave frequencies

thereby mitigating their impact on noise

gain

and stability. Measurement results show that the proposed LNA achieves a peak gain of 16.8 dB

a 3 dB bandwidth of 8.8 GHz over 21.5~30.3 GHz

and a minimum NF of 3.26 dB. The measured IP

1 dB

reaches -3.6 dBm

while the core area is only 0.11 mm². These results demonstrate that the proposed design effectively improves the noise-linearity-gain trade-off and provides a promising solution for high-dynamic-range millimeter-wave receiver front ends.

关键词

Keywords

references

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