SHI Wei, CHEN Fang-yuan, WANG Zhi-ying, et al. Design and VLSI Implementation of an Asynchronous Microprocessor Based on Transport Triggered Architecture[J]. Acta Electronica Sinica, 2011, 39(2): 395-401.
SHI Wei, CHEN Fang-yuan, WANG Zhi-ying, et al. Design and VLSI Implementation of an Asynchronous Microprocessor Based on Transport Triggered Architecture[J]. Acta Electronica Sinica, 2011, 39(2): 395-401.DOI:
The design of an asynchronous pipelined microprocessor based on transport triggered architecture is introduced.The distributed control in the asynchronous TTA microprocessor
the data dependence might give rise to a wrong result of the executed program.A data source select scheme is proposed to guarantee instructions running correctly on the asynchronous TTA microprocessor.The micro-architecture of the proposed asynchronous processor is presented
and an asynchronous microprocessor is implemented in an 180nm technology.The experimental results show that the implemented asynchronous microprocessor can run correctly
and the asynchronous circuit style can offer a low power solution for future microprocessor design.The power dissipation of asynchronous TTA core takes only about 40% of the synchronous equivalent.