基于DPU的机载射频综合处理系统研究与设计

马城城; 田泽; 郭玄瀛; 张琛; 梁军利; 郑江滨; 王保平; 刘博; 李林泽; 刘小旗

doi:10.12263/DZXB.20260056

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基于DPU的机载射频综合处理系统研究与设计

面向高效人工智能的新型架构与电子系统 | 更新时间：2026-10-16

- 基于DPU的机载射频综合处理系统研究与设计
- Research and Design of a DPU-Based Airborne Integrated RF Processing System
- 电子学报 2026年54卷第6期页码：2454-2467
- 作者机构：
  
  1.西北工业大学，陕西西安 710072
  2.西安翔腾微电子科技有限公司，陕西西安 710072
  3.集成电路与微系统设计航空科技重点实验室，陕西西安 710072
  4.陕西省空天智算与算力网络重点实验室，陕西西安 710072
- 作者简介：
  
  马城城男，1988年9月出生于陕西省铜川市。现为西安翔腾微电子科技有限公司智能计算与算力网络方向负责人。主要研究方向为智能计算、算力网络、SoC设计与验证。E-mail: mccheng@mail.nwpu.edu.cn
  田泽男，1965年11月出生于陕西省宝鸡市。博士，研究员，中国航空工业集团首席技术专家。主要研究方向为SoC设计、嵌入式系统设计、VLSI设计等。E-mail: tarmz@126.com
  郭玄瀛男，1994年10月出生于山西省晋城市。现为西安翔腾微电子科技有限公司助理研究员。主要研究方向为射频综合计算技术及网络技术。E-mail: 415036790@qq.com
  张琛女，1989年6月出生于陕西省渭南市。现为西安翔腾微电子科技有限公司助理研究员。主要研究方向算力及算力网络芯片设计。E-mail: zchen.xtic@qq.com
  梁军利男，1978年6月出生于陕西省咸阳市。现为西北工业大学教授、博士生导师。主要研究方向为雷达波形设计、阵列信号处理、非凸优化、6G、机器学习等。E-mail: liangjunli@nwpu.edu.cn
  郑江滨男，1971年11月出生于陕西省西安市。现为西北工业大学教授、博士生导师。主要研究方向为计算机视觉、嵌入式移动媒体处理技术及图像处理与模式识别等。E-mail: zhengjb@nwpu.edu.cn
  王保平男，1964年5月出生于陕西省西安市。现为西北工业大学教授、博士生导师。主要研究方向为计算机体系结构和软件、人工智能、集成电路与微系统等。E-mail: baoping-wang@nwpu.edu.cn
  刘博男，1996年12月出生于陕西省宝鸡市。现为西安翔腾微电子科技有限公司助理研究员。主要研究方向为嵌入式DPU驱动开发及其在高性能网络通信场景中的应用。E-mail: shliu1461@163.com
  李林泽男，1996年11月出生于陕西省延安市。现为西安翔腾微电子科技有限公司助理研究员。主要研究方向为无损以太网。E-mail: Lxillz@163.com
  刘小旗女，1996年8月出生于山西省吕梁市。现为西安翔腾微电子科技有限公司助理研究员。主要研究方向为嵌入式实时系统适配、网络管理、高精度时间同步等。E-mail: 1483764748@qq.com
- 基金信息：
- DOI：10.12263/DZXB.20260056
  中图分类号： TP303;V243
- 收稿：2026-04-23，
  
  录用：2026-05-19，
  
  纸质出版：2026-06-25
- 稿件说明：
移动端阅览
马城城, 田泽, 郭玄瀛, 等. 基于DPU的机载射频综合处理系统研究与设计[J]. 电子学报, 2026, 54(06): 2454-2467.

MA Chengcheng, TIAN Ze, GUO Xuanying, et al. Research and Design of a DPU-Based Airborne Integrated RF Processing System[J]. Acta Electronica Sinica, 2026, 54(06): 2454-2467.
马城城, 田泽, 郭玄瀛, 等. 基于DPU的机载射频综合处理系统研究与设计[J]. 电子学报, 2026, 54(06): 2454-2467. DOI：10.12263/DZXB.20260056

MA Chengcheng, TIAN Ze, GUO Xuanying, et al. Research and Design of a DPU-Based Airborne Integrated RF Processing System[J]. Acta Electronica Sinica, 2026, 54(06): 2454-2467. DOI：10.12263/DZXB.20260056

摘要

机载射频（Radio Frequency，RF）系统正朝着智能蒙皮、多功能综合与智能化方向快速演进，系统数据规模、算力需求及产品迭代速度呈指数级增长。当前的基于SRIO互联的FPGA+DSP定制计算架构存在计算资源与任务强耦合、异构算力难以高效聚合以及系统扩展性受限等问题，已难以支撑新一代机载射频处理需求。为突破上述瓶颈，本文借鉴主流智算中心的计算架构理念，将其引入机载射频计算领域，提出了一种基于数据处理单元（Data Processing Unit，DPU）的射频综合处理系统。该系统采用IEEE 1588v2与同步以太网（Synchronous Ethernet，SyncE）协同的高精度时钟同步机制，解决了弹性分布式架构下多源射频海量数据的高精度时空对齐问题；基于远程内存直接访问（Remote Direct Memory Access，RDMA）实现领域特定架构数据直通（Domain-Specific Architecture Direct，DSA Direct）技术，支持数据从采集、处理到存储的端到端零拷贝传输，显著降低系统传输时延；通过融合PCIe与RDMA的异构算力互联机制，实现统一内存视图下的异构算力聚合与灵活配置。依托纳秒级同步接入、异构算力协同计算与分布式存储能力，构建了以数据为中心的射频综合处理体系。该体系由射频接入节点与异构算力资源池组成，通过高速以太网交换机互联，将智能、并行、通用和可重构四类异构算力节点及NVMe-oF（NVMe over Fabrics）分布式存储节点统一纳入算力网络，支持面向任务的弹性资源组合与动态部署。基于国产DPU FPGA原型，搭建了射频综合处理系统实验环境，并针对多通道射频数据接入、跨节点异构算力协同与分布式存储访问等典型数据流进行了验证。测试结果表明：相较于当前架构，该系统在数据传输延迟方面单次拷贝延迟约降至原来的1/360；NVMe-oF存储节点三盘顺序读写峰值带宽超过5 700 MB/s，较当前方式性能提升6到8倍；基于IEEE 1588v2+SyncE的时钟同步精度为8.33 ns。此外，通过构建典型雷达与通信信号处理链路，其中雷达场景下128 MB雷达原始数据接入延迟低至24.92 ms，通信场景下可稳定承载38路并行基带数据流实时接入，验证了系统在高吞吐原始数据注入及多级异构计算中的实时业务承载能力。实验证明，该架构为新一代机载射频综合处理系统提供了一种切实可行的技术路径。

Abstract

Airborne radio frequency (RF) systems are rapidly evolving toward intelligent skins

multifunctional integration

and intelligence

with exponential growth in system data volume

computational demands

and product iteration speed. Conventional FPGA+DSP custom computing architectures base

d on SRIO interconnection suffer from strong coupling between computing resources and tasks

inefficient aggregation of heterogeneous computing power

and limited system scalability

making them inadequate to support the requirements of next-generation airborne RF processing. To overcome these bottlenecks

this paper draws on the computational architecture concepts of mainstream intelligent computing centers and introduces them into the airborne RF computing domain

proposing a data processing unit (DPU)-based integrated RF processing system. This system employs a high-precision clock synchronization mechanism combining IEEE 1588v2 and synchronous ethernet (SyncE)

addressing the high-precision spatiotemporal alignment of massive multi-source RF data in elastic distributed architectures. Based on remote direct memory access (RDMA)

domain-specific architecture direct (DSA Direct) data passthrough is implemented

supporting end-to-end zero-copy transmission from data acquisition and processing to storage

significantly reducing system transmission latency. Through a heterogeneous computing power interconnection mechanism integrating PCIe and RDMA

aggregation and flexible configuration of heterogeneous computing power under a unified memory view are achieved. Leveraging nanosecond-level synchronous access

collaborative heterogeneous computing

and distributed storage capabilities

a data-centric integrated RF processing architecture is constructed. The architecture consists of RF access nodes and a heterogeneous computing resource pool interconnected through high-speed Ethernet switches

integrating intelligent

parallel

general-purpose

and reconfigurable heterogeneous computing nodes together with NVMe-oF distributed storage nodes into a unified computing power network

thereby supporting task-oriented elastic resource composition and dynamic deployment. Using a domestic DPU FPGA prototype

an experimental environment for the integrated RF processing system was established

and typical data flows including mul

ti-channel RF data access

cross-node heterogeneous computing collaboration

distributed storage access

as well as RF data transmission

storage

and computation were validated. Test results indicate that compared to conventional architectures

the system reduces single-copy latency in data transmission to approximately 1/360 of the original; the peak sequential read/write bandwidth of NVMe over fabrics

(

NVMe-oF) storage nodes with three disks exceeds 5 700  MB/s

representing a 6 to 8 fold performance improvement over conventional methods; and the clock synchronization accuracy based on IEEE 1588v2+SyncE is approximately 8.33 ns. Furthermore

by constructing typical radar and communication signal processing chains

the system demonstrated an access latency as low as 24.92 ms for 128 MB radar raw data in the radar scenario

while stably supporting the real-time access of 38 parallel baseband data streams in the communication scenario

thereby validating its real-time service capability under high-throughput raw data injection and multi-level heterogeneous computing. Experiments demonstrate that this architecture provides a feasible technical pathway for next-generation airborne integrated RF processing systems.

关键词

Keywords

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