基于逐级位宽递增优化的高效流水线CORDIC硬件设计

马昕; 刘胜; 吴振宇; 常俊胜; 原博

doi:10.12263/DZXB.20260320

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基于逐级位宽递增优化的高效流水线CORDIC硬件设计

更新时间：2026-10-13

- 基于逐级位宽递增优化的高效流水线CORDIC硬件设计
- Efficient Pipelined CORDIC Hardware Design Based on Stepwise Word-Length Increment Optimization
- 电子学报 2026年页码：1-14
- 作者机构：
  
  1.国防科技大学计算机学院，湖南长沙 410073
  2.先进微处理器芯片与系统重点实验室（国防科技大学），湖南长沙 410073
- 作者简介：
  
  马昕女，1999年3月出生于山东省青岛市。现为国防科技大学计算机学院硕士研究生。主要研究方向为微处理器设计与低功耗设计方法。E-mail: xinma@nudt.edu.cn
  刘胜男，1984年1月出生于河南省南阳市。现为国防科技大学计算机学院研究员。主要研究方向为微处理器体系结构和VLSI设计。E-mail: liusheng83@nudt.edu.cn
  吴振宇男，1991年7月出生于浙江省衢州市。现为国防科技大学计算机学院助理研究员。主要研究方向为低功耗设计方法学与高能效微处理器设计。E-mail: wuzhenyu@nudt.edu.cn
  常俊胜男，1979年8月出生于河南省南阳市。现为国防科技大学计算机学院研究员。主要研究方向为计算机体系结构、高速互连网络。E-mail: junshengchang@nudt.edu.cn
  原博男，1996年8月出生于陕西省咸阳市。现为国防科技大学计算机学院博士研究生。主要研究方向为微处理器体系结构和VLSI设计。E-mail: yuanbol8@nudt.edu.cn
- 基金信息：
  
  国家“万人计划”青年拔尖人才支持计划(ZC514C0882503)
- DOI：10.12263/DZXB.20260320
  中图分类号： TN492;TP302
- 收稿：2026-08-04，
  
  录用：2026-08-30，
  
  网络首发：2026-10-13，
- 稿件说明：
移动端阅览
马昕, 刘胜, 吴振宇, 等. 基于逐级位宽递增优化的高效流水线CORDIC硬件设计[J/OL]. 电子学报, 2026,1-14.

MA Xin, LIU Sheng, WU Zhenyu, et al. Efficient Pipelined CORDIC Hardware Design Based on Stepwise Word-Length Increment Optimization[J/OL]. ACTA ELECTRONICA SINICA, 2026, 1-14.
马昕, 刘胜, 吴振宇, 等. 基于逐级位宽递增优化的高效流水线CORDIC硬件设计[J/OL]. 电子学报, 2026,1-14. DOI： 10.12263/DZXB.20260320.

MA Xin, LIU Sheng, WU Zhenyu, et al. Efficient Pipelined CORDIC Hardware Design Based on Stepwise Word-Length Increment Optimization[J/OL]. ACTA ELECTRONICA SINICA, 2026, 1-14. DOI： 10.12263/DZXB.20260320.

摘要

坐标旋转数字计算（CoOrdinate Rotation DIgital Computer， CORDIC）算法利用移位和加减运算实现多类函数计算，具有结构规则、易于流水化等特点，广泛应用于数字信号处理、通信和嵌入式系统等领域。但随着应用规模与计算精度的提高，系统设计面临兼顾高吞吐率与低硬件开销的严峻挑战。传统流水线CORDIC实现通常采用预缩放初值，并在各迭代级配置统一最大位宽，导致迭代初期尚未产生有效低位数据时仍实例化全字长硬件，存在显著的硬件开销。针对这一问题，本文提出一种基于逐级位宽递增优化与重定时技术的高效流水线CORDIC架构。首先，采用整数初始化并将固定缩放因子补偿外置或后置的方法，解除预缩放方式对数据通路的全字长约束，在此基础上，通过分析移位加减过程中低位有效信息的生成特征，建立逐级位宽递增模型。理论分析表明，在达到目标位宽前，数据有效位宽随迭代次数呈二次增长，据此按需裁剪前序迭代级数据通路的寄存器和移位加法器，使迭代初期仅实例化覆盖当前有效信息的逻辑资源，在保持基本微旋转形式和计算精度不变的条件下降低硬件开销。其次，针对非均匀位宽导致的级间延迟不平衡问题，对数据通路关键路径进行分析，并利用前序低位宽流水级的时序裕量，引入低位宽流水级合并与重定时优化，进一步减少流水寄存器及相关面积、功耗开销。实验结果表明，在8位有符号定点数据格式下，与统一位宽CORDIC相比，该架构使电路面积减少16.72%，逻辑单元数量减少22.23%，功耗降低13.97%，结合流水级合并与重定时后，相比未重定时的统一位宽CORDIC，面积减少33.2%，功耗降低20%。该架构在不同精度配置下均保持显著优势，具有良好的可扩展性。该方法还可扩展至采用整数或低精度常数初始化、保持移位加减迭代形式且缩放补偿可外置的其他CORDIC变体，为高吞吐、资源受限的数字信号处理系统提供低面积、低功耗的CORDIC硬件实现方案。

Abstract

Coordinate rotation digital computer (CORDIC) algorithms implement a wide range of function evaluations using shift and add/subtract operations. Owing to their regular structures and natural suitability for pipelining

CORDIC architectures have been widely used in digital signal processing

communication

and embedded systems. However

with the increasing application scale and computational precision

achieving both high throughput and low hardware overhead has become increasingly challenging. Conventional pipelined CORDIC implementations generally employ prescaled initial values and a uniform maximum word length across all iteration stages. As a result

full-word-length hardware is still instantiated in the early iterations even though valid low-order data have not yet been generated

leading to considerable redundant hardware overhead. To address this problem

this paper proposes an efficient pipelined CORDIC architecture based on stepwise word-length increment optimization and retiming.First

integer initialization is adopted

while compensation for the fixed scaling factor is moved outside the core datapath or deferred to a post-processing stage

thereby removing the full-word-length constraint imposed by prescaling. On this basis

the generation characteristics of valid low-order information during shift-add iterations are analyzed

and a stepwise word-length increment model is established. Theoretical analysis shows that

before the target word length is reached

the effective word length increases quadratically with the iteration index. According to this model

the registers and shift-adders in the

and

atapaths of the early iteration stages are trimmed on demand

so that only the logic resources required to represent the currently effective information are instantiated in the early iterations. In this way

hardware overhead is reduced while preserving the basic micro-rotation form and computational accuracy of the original CORDIC algorithm.Second

to address the inter-stage delay imbalance caused by the nonuniform word-length distribution

the critical paths of the datapath are analyzed. Since the early low-word-length pipeline stages exhibit shorter carry-propagation paths and therefore larger timing slack

low-word-length pipeline stage merging and retiming optimization are introduced to exploit this slack. By merging adjacent early pipeline stages and redistributing pipeline registers through retiming

the proposed architecture further reduces pipeline-register overhead as well as the associated area and power consumption.Experimental results show that

under an 8-bit signed fixed-point configuration

the proposed stepwise word-length increment architecture reduces circuit area by 16.72%

the total number of logic cells by 22.23%

and power consumption by 13.97% compared with the uniform-word-length CORDIC. With low-word-length pipeline stage merging and retiming

the area and power consumption are further reduced by 33.2% and 20%

respectively

compared with the unretimed uniform-word-length CORDIC. The proposed architecture also maintains significant area advantages under different precision configurations

demonstrating good scalability. In addition

the proposed method can be extended to other CORDIC variants that adopt integer or low-precision constant initialization

retain shift-add-based iterative updates

and allow scaling-factor compensation to be performed outside the core datapath. Therefore

the proposed architecture provides a low-area and low-power CORDIC hardware implementation for high-throughput and resource-constrained digital signal processing systems.

关键词

Keywords

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