基于参数化模型的FPGA时钟网络设计和优化

doi:10.3969/j.issn.0372-2112.2017.07.019

电子学报 ›› 2017, Vol. 45 ›› Issue (7): 1686-1694.DOI: 10.3969/j.issn.0372-2112.2017.07.019

基于参数化模型的FPGA时钟网络设计和优化

余乐¹, 陈岩¹, 李洋洋¹, 吴超¹, 王瑶¹, 苏童¹, 谢元禄²

1. 北京工商大学计算机与信息工程学院食品安全大数据技术北京市重点实验室, 北京 100048;
2. 中国科学院微电子学研究所中国科学院微电子器件与集成技术重点实验室, 北京 100049

收稿日期:2016-06-13 修回日期:2016-12-09 出版日期:2017-07-25
- 作者简介:
- 余乐(通信作者),男,1983年6月生于湖北黄冈,现为北京工商大学计算机与信息工程学院讲师.现在的研究兴趣:计算视觉与类脑芯片.E-mail:yule@btbu.edu.cn;陈岩,女,1963年7月生于黑龙江哈尔滨,现为北京工商大学计算机与信息工程学院教授,研究方向:无线传感器网络技术应用、数字通信抗干扰技术.
- 基金资助:
- 北京市自然科学基金 (No.4174086）

Design and Optimization of FPGA Clock Network Based on Parameterized Model

YU Le¹, CHEN Yan¹, LI Yang-yang¹, WU Chao¹, WANG Yao¹, SU Tong¹, XIE Yuan-lu²

1. Beijing Key Laboratory of Big Data Technology for Food Safety, School of Computer and Information Engineering, Beijing Technology and Business University, Beijing 100048, China;
2. Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100049, China

Received:2016-06-13 Revised:2016-12-09 Online:2017-07-25 Published:2017-07-25

摘要/Abstract

摘要：

本文在FPGA时钟网络（Clock Distributed Network，CDN）关键结构尺寸的参数化建模基础上，提出一种针对全定制FPGA CDN的设计和优化方法.本文所建立的参数化模型将结构尺寸分为拓扑结构和电路与互连两类，分别给出了这两类尺寸参数的设计原则.在标准CMOS 0.13μm工艺下，对H树型、鱼骨型以及混合型三种类型时钟网络设计了2组结构参数，分别代表优化前和优化后，对比分析延时、偏斜、功耗和面积等性能参数.实验结果显示：混合型结构在绝对延时和时钟偏斜上减小最多，分别达到20.89%和63.20%；鱼骨型结构的面积减小达到50.14%；H树型结构的绝对延时和功耗则均降低了7.37%和8.33%.以上结果充分证明了本文所提设计优化方法的有效性.

关键词: FPGA, 时钟网络, 参数化, 建模

Abstract:

This paper proposes a methodology for the design and optimization of CDN (Clock Distributed Network) in full custom FPGA systems based on parameterized models of the structural sizes of the key components of CDN systems.The characteristic model proposed herein divides structural sizes into two categories:topology structure,and circuit and interconnect,and provides the design methodology of these two types of sizes.The paper establishes two sets of structure parameters for H-tree,fish-bone and mixed clock networks in standard CMOS 0.13 μm technology,each representing CDN with or without optimizations.And then we compares the performance in terms of transmission delay,clock skew,power consumption,chip area,among a multitude of other parameters.Experiment results indicate that mixed structure results in the greatest reductions of transmission delay and clock skew by 20.89% and 63.20%,respectively;fish-bone structure achieves the best reductions in chip area by 50.14%,while H-tree structure reduces in transmission delay and power consumption by 7.37% and 8.33%,respectively,which strongly confirms the proposed design and optimization methodology.

Key words: FPGA, clock distributed network (CDN), parameterized, modeling

中图分类号:

TP391

余乐, 陈岩, 李洋洋, 吴超, 王瑶, 苏童, 谢元禄. 基于参数化模型的FPGA时钟网络设计和优化[J]. 电子学报, 2017, 45(7): 1686-1694.

YU Le, CHEN Yan, LI Yang-yang, WU Chao, WANG Yao, SU Tong, XIE Yuan-lu. Design and Optimization of FPGA Clock Network Based on Parameterized Model[J]. Acta Electronica Sinica, 2017, 45(7): 1686-1694.

参考文献

[1] E G Friedman.Clock distribution networks in synchronous digital integrated circuits[J].Proceedings of the IEEE,2001,89(5):665-692.
[2] M A El-Moursy,E G Friedman.Exponentially tapered H-tree clock distribution networks[J].IEEE Transactions on Very Large Scale Integration Systems (TVLSI),2005,13(8):971-975.
[3] J Rosenfeld,E G Friedman.Design methodology for global resonant H-tree clock distribution networks[J].IEEE Transactions on Very Large Scale Integration Systems(TVLSI),2007,15(2):135-148.
[4] A Rajaram,D Z Pan.Meshworks:A com-prehensive framework for optimized clock mesh network synthesis[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),2010,29(12):1945-1958.
[5] Wei-Khee Loo,Kok-Siang Tan,Ying-Khai Teh.A study and design of CMOS H-tree clock distribution network in system-on-chip[A].IEEE 8th International Conference on ASIC (ASICON)[C].Changsha,China,2009.411-414.
[6] Xilinx Corporation.Virtex7 Datasheet[EB/OL].http://www.xilinx.com/support/documentation/data_sheets/ds183_Virtex_7_Data_Sheet.pdf,2012.
[7] Yu Le,Sun Jiabin,Chen Zhujia,et al.A design methodology for low-leakage and high-performance buffer based on deviant behavior of gate leakage[J].Journal of Electronics (China),2014,31(5):411-415.
[8] Yang Haigang,Zhang Jia,Sun jiabin,Yu Le.Review of advanced FPGA architectures and technologies[J].Journal of Electronics (China),2014,31(5):371-393.
[9] Altera Corporation.Stratix Device Handbook[EB/OL].https://www.altera.com.cn/zh_CN/pdfs/literature/hb/stx/ch_11_vol_2.pdf,2005.
[10] Xilinx Corporation.Xilinx 7 Series FPGAs Clock Network[EB/OL].https://china.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf,2016.
[11] Altera Corporation.Stratix V Device Handbook[EB/OL].https://www.alteracom.cn/en_US/pdfs/literature/hb/stratix-v/stx5_core.pdf,2016.
[12] Kara K W Poon,Steven J E Wilton,Andy Yan,et al.A detailed power model for field-programmable gate arrays[J].ACM Transactions on Design Automation of Electronic Systems (TODAES),2005,(10)2:279-302.
[13] J Lamoureux,S J E Wilton.FPGA clock network architecture:flexibility vs area and power[A].Symposium on Field Programmable Gate Arrays (FPGA)[C].Monterey,USA,2006.101-108.
[14] J.Lamoureux,S J E Wilton.Clock-aware placement for FPGAs[A].IEEE International Conference on Field Programmable Logic and Applications (FPL)[C].Amsterdam,2007.124-131.
[15] S Huda,M Mallick,J H Anderson,et al.Clock gating architectures for FPGA power reduction[A].IEEE International Conference on Field Programmable Logic and Applications (FPL)[C].Prague,Czech Republic,2009.112-118.
[16] P Sedcole,J S Wong,P Y K Cheung.Characterization of FPGA Clock Variability[A].IEEE Computer Society Annual Symposium on VLSI (ISVLSI)[C].Montpellier,France,2008.322-328.
[17] P Sedcole,J S Wong,P Y K Cheung.Modelling and compensating for clock skew variability in FPGAs[A].International Conference on Field Programmable Techology (ICFPT)[C].Taipei,2008.217-224.
[18] G Lhairech-Lebreton,P Coussy,E Martin.Hierarchical and multiple-clock domain high-level synthesis for low-power design on FPGA[A].International Conference on Field Programmable Logic and Applications (FPL)[C].Milano,Italy,2010.464-468.
[19] Loh Siang Poh,Lim Chooi Pei.Hybrid clock network for altera structure ASIC devices[A].IEEE International Conference on Semiconductor Electronics (ICSE)[C].Leipzig,Germany,2008.23-26.
[20] A Rakhshanfar,J H Anderson.An integer programming placement approach to FPGA clock power reduction[A].16th Asia and South Pacific Design Automation Conference (ASP-DAC)[C].Pacifico Yokohama,JP,2011.831-836.

基于参数化模型的FPGA时钟网络设计和优化

Design and Optimization of FPGA Clock Network Based on Parameterized Model

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

[1]	邓海刚, 王传旭, 李成伟, 林晓萌. 深度学习框架下群组行为识别算法综述[J]. 电子学报, 2022, 50(8): 2018-2036.
[2]	袁海英, 曾智勇, 成君鹏. 面向灵活并行度的稀疏卷积神经网络加速器[J]. 电子学报, 2022, 50(8): 1811-1818.
[3]	任莎莎, 刘琼. 小目标特征增强图像分割算法[J]. 电子学报, 2022, 50(8): 1894-1904.
[4]	陈晓杰, 李斌, 周清雷. RTL级可扩展高性能数据压缩方法实现[J]. 电子学报, 2022, 50(7): 1548-1557.
[5]	刘文杰, 赵胶胶, 张颖, 葛业波. 一种量子条件生成对抗网络算法[J]. 电子学报, 2022, 50(7): 1586-1593.
[6]	许皓文, 陆浩, 王振占. 高光谱微波辐射计系统中2GHz带宽数字谱仪设计[J]. 电子学报, 2022, 50(6): 1472-1479.
[7]	曲立国, 陈国豪, 胡俊, 陈鹏. 单次扫描连通域分析算法研究综述[J]. 电子学报, 2022, 50(6): 1521-1536.
[8]	王鹏, 邹彬, 刘金枝, 周丹阳. 基于Xilinx型FPGA系统单粒子效应评估方法研究[J]. 电子学报, 2022, 50(11): 2716-2721.
[9]	李斌, 齐延荣, 周清雷. 基于Winograd算法的目标检测加速器设计与优化[J]. 电子学报, 2022, 50(10): 2387-2397.
[10]	蔡莹, 朱翔, 王舰, 李昊远, 韩建伟. 基于激光注入的FPGA加密防护设计验证研究[J]. 电子学报, 2022, 50(10): 2381-2386.
[11]	赵雄文, 张钰, 秦鹏, 王晓晴, 耿绥燕, 宋俊元, 刘瑶, 李思峰. 空天地一体化无线光通信网络关键技术及其发展趋势[J]. 电子学报, 2022, 50(1): 1-17.
[12]	王相海, 宋若曦, 曲思洁, 穆振华, 宋传鸣. 图像多尺度几何分析域隐马尔可夫树模型研究进展[J]. 电子学报, 2022, 50(1): 238-249.
[13]	陶凌, 陈安庆, 邓贞宙, 韩春雷, 王玉皞, 王平. 应用分形几何与混沌理论进行植物形态建模[J]. 电子学报, 2021, 49(9): 1776-1782.
[14]	王伟, 于磊, 任国恒, 陈立勇, 董秋雷, 胡占义. 城市建筑立面三维“线-面”结构快速重建[J]. 电子学报, 2021, 49(8): 1551-1560.
[15]	魏光辉, 杜雪, 王雅平. 用频设备带外多频电磁辐射三阶互调阻塞效应测试与建模评估方法[J]. 电子学报, 2021, 49(6): 1094-1100.