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多核实时线程间干扰分析及WCET估值

陈芳园1, 张冬松1,2, 王志英1   

  1. 1. 国防科学技术大学计算机学院, 湖南长沙 410073;
    2. 国防科学技术大学并行与分布处理国家重点实验室, 湖南长沙 410073
  • 收稿日期:2011-08-01 修回日期:2012-02-21 出版日期:2012-07-25 发布日期:2012-07-25
  • 作者简介:陈芳园 女,1982年生,湖北钟祥人.博士生.主要研究领域为实时系统和计算机体系结构. E-mail:fychen@nudt.edu.cn 张冬松 男,1980年生,河南信阳人.博士生.CCF学生会员.主要研究领域为实时系统和低功耗嵌入式系统. 王志英 男,1956年生,湖南长沙人.教授,博士生导师.主要研究领域为计算机体系结构、高性能微处理器设计和嵌入式系统.
  • 基金资助:

    国家教育部博士点基金(No.20104307110005);国防科学技术大学优秀研究生创新资助(No.B100601);湖南省研究生科研创新项目资助(No.CX2010B026)

Inter-Thread Interference Analysis for Real-Time WCET Estimations of Multi-Core Architectures

CHEN Fang-yuan1, ZHANG Dong-song1,2, WANG Zhi-ying1   

  1. 1. College of Computer, National University of Defense Technology, Changsha, Hunan 410073, China;
    2. National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha, Hunan 410073, China
  • Received:2011-08-01 Revised:2012-02-21 Online:2012-07-25 Published:2012-07-25

摘要: 在共享Cache的多核处理器中,线程在共享Cache中的指令可能被其他并行线程的指令替换,从而导致了线程间在共享Cache上的干扰.多核结构下WCET估值需要考虑并行线程间在共享Cache上的干扰.针对当前典型的共享Cache和共享总线的多核结构,本文提出了一种迭代的WCET估值分析方法.考虑共享总线对共享Cache访问的时序影响,基于该时序分析线程间在共享Cache上的干扰,得到较精确的WCET估值.理论分析证明了该方法的有效性,实验结果表明本文的分析方法较之当前的两种方法分别可以提高21%和14%的精确度.

关键词: 多核体系结构, 共享Cache, 共享总线, 干扰, WCET

Abstract: In a shared-cache multi-core architecture one thread may interfere with a second thread if the second one tries to access the shared cache simultaneously.Consequently,this causes the eviction of the second thread instructions.To track this challenge,designers need to consider runtime inter-thread interference while analyzing WCET of a real-time application on multi-core architectures.This paper proposes an iterative approach for WCET estimation which considers the circular dependence between shared bus and the runtime inter-thread interference in shared cache.Our approach analyzes inter-thread interference in shared cache based on access timings,which combines static analysis and dynamic timing estimation.The iterative method presented can improve the tightness of WCET estimation by refining estimations of inter-thread interference.Our experiments demonstrate that the proposed approach can reasonably estimate inter-thread interference in shared caches and improve the tightness of WCET estimation by an average of 21% and 14%,compared with the estimations in literatures.

Key words: multi-core architecture, shared cache, shared bus, interference, WCET

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