一种3D堆叠集成电路中间绑定测试时间优化方案

doi:10.3969/j.issn.0372-2112.2015.02.029

电子学报 ›› 2015, Vol. 43 ›› Issue (2): 393-398.DOI: 10.3969/j.issn.0372-2112.2015.02.029

一种3D堆叠集成电路中间绑定测试时间优化方案

常郝^1,3, 梁华国², 蒋翠云⁴, 欧阳一鸣¹, 徐辉¹

1. 合肥工业大学计算机与信息学院, 安徽合肥, 230009;
2. 合肥工业大学电子科学与应用物理学院, 安徽合肥, 230009;
3. 安徽财经大学计算机科学与技术系, 安徽蚌埠, 233030;
4. 合肥工业大学数学学院, 安徽合肥, 230009

收稿日期:2013-12-26 修回日期:2014-06-19 出版日期:2015-02-25
- 作者简介:
- 常郝 男,1983年9月生于安徽寿县.现为合肥工业大学计算机应用专业博士研究生,安徽财经大学计算机系讲师,主要研究方向为三维堆叠集成电路测试技术,内建自测试(BIST). E-mail:007changhao@163.com;梁华国 男,1959年生于安徽合肥,教授,博士生导师,主要研究方向为内建自测试、数字系统设计自动化、ATPG算法、分布式控制等. E-mail:huagulg@hfut.edu.cn
- 基金资助:
- 国家自然科学基金 (No.61274036,No.61371025,No.61204046,No.61474036)

Optimization Scheme for Mid-bond Test Time on 3D-Stacked ICs

CHANG Hao^1,3, LIANG Hua-guo², JIANG Cui-yun⁴, OUYANG Yi-ming¹, XU Hui¹

1. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230009, China;
2. School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei, Anhui 230009, China;
3. School of Management Science and Engineering, Anhui University of Finance and Economics, Bengbu, Anhui 233030, China;
4. School of Mathematics, Hefei University of Technology, Hefei, Anhui 230009, China

Received:2013-12-26 Revised:2014-06-19 Online:2015-02-25 Published:2015-02-25

摘要/Abstract

摘要：

中间绑定测试能够更早地检测出3D堆叠集成电路绑定过程引入的缺陷,但导致测试时间和测试功耗剧增.考虑测试TSV、测试管脚和测试功耗等约束条件,采用整数线性规划方法在不同的堆叠布局下优化中间绑定测试时间.与仅考虑绑定后测试不同,考虑中间绑定测试时,菱形结构和倒金字塔结构比金字塔结构测试时间分别减少4.39%和40.72%,测试TSV增加11.84%和52.24%,测试管脚减少10.87%和7.25%.在测试功耗约束下,金字塔结构的测试时间增加10.07%,而菱形结构和倒金字塔结构测试时间只增加4.34%和2.65%.实验结果表明,菱形结构和倒金字塔结构比金字塔结构更具优势.

关键词: 三维堆叠集成电路, 中间绑定测试, 硅通孔, 测试访问机制, 整数线性规划

Abstract:

Mid-bond test can detect the defects introduced in the bonding process earlier,which will also result in the significant growth of the test application time and test power consumption.Considering the test TSVs,test pins and power consumption,Integer Linear Programming was used to optimize the test application time under three stack structures.Different from the post bond test,compared with the Pyramid structure,the test application time decreases by 4.39% and 40.72%,the number of test TSV increases by 11.84% and 52.24%,the number of test pin reduces by 10.87% and 7.25% in the diamond structure and the inverted Pyramid structure respectively.Considering the test power consumption,the test application time increases by 10.07% in the Pyramid structure,while the diamond structure and the inverted Pyramid structure only increase by 4.34% and 2.65%.The experimental results show that the diamond structure and the inverted Pyramid structure have greater advantage over the Pyramid structure in the mid-bond test.

Key words: 3D stacked ICs, mid-bond test, through silicon via (TSV), test access mechanism (TAM), integer linear programming (ILP)

中图分类号:

TP306.2

常郝, 梁华国, 蒋翠云, 欧阳一鸣, 徐辉. 一种3D堆叠集成电路中间绑定测试时间优化方案[J]. 电子学报, 2015, 43(2): 393-398.

CHANG Hao, LIANG Hua-guo, JIANG Cui-yun, OUYANG Yi-ming, XU Hui. Optimization Scheme for Mid-bond Test Time on 3D-Stacked ICs[J]. Acta Electronica Sinica, 2015, 43(2): 393-398.

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一种3D堆叠集成电路中间绑定测试时间优化方案

Optimization Scheme for Mid-bond Test Time on 3D-Stacked ICs

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