Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology

HUANG Zheng-feng, PAN Shang-jie, CAO Jian-fei, SONG Tai, OUYANG Yi-ming, LIANG Hua-guo, NI Tian-ming, LU Ying-chun

Acta Electronica Sinica ›› 2021, Vol. 49 ›› Issue (2) : 394-400.

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Acta Electronica Sinica ›› 2021, Vol. 49 ›› Issue (2) : 394-400. DOI: 10.12263/DZXB.20200530
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Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2021, 49(2): 394-400 https://doi.org/10.12263/DZXB.20200530

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