Via-Aware Parallel Layer Assignment Algorithm for VLSI Physical Design

LIU Geng-geng, LI Ze-peng, GUO Wen-zhong, CHEN Guo-long, XU Ning

ACTA ELECTRONICA SINICA ›› 2022, Vol. 50 ›› Issue (11) : 2575-2583.

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ACTA ELECTRONICA SINICA ›› 2022, Vol. 50 ›› Issue (11) : 2575-2583. DOI: 10.12263/DZXB.20211065
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Via-Aware Parallel Layer Assignment Algorithm for VLSI Physical Design

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2022, 50(11): 2575-2583. https://doi.org/10.12263/DZXB.20211065

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