Via-Aware Parallel Layer Assignment Algorithm for VLSI Physical Design

LIU Geng-geng, LI Ze-peng, GUO Wen-zhong, CHEN Guo-long, XU Ning

Acta Electronica Sinica ›› 2022, Vol. 50 ›› Issue (11) : 2575-2583.

PDF(2621 KB)
CIE Homepage  |  Join CIE  |  Login CIE  |  中文 
PDF(2621 KB)
Acta Electronica Sinica ›› 2022, Vol. 50 ›› Issue (11) : 2575-2583. DOI: 10.12263/DZXB.20211065
PAPERS

Via-Aware Parallel Layer Assignment Algorithm for VLSI Physical Design

    {{javascript:window.custom_author_en_index=0;}}
  • {{article.zuoZhe_EN}}
Author information +

HeighLight

{{article.keyPoints_en}}

Abstract

{{article.zhaiyao_en}}

Key words

QR code of this article

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations
{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2022, 50(11): 2575-2583 https://doi.org/10.12263/DZXB.20211065

References

Publishing order | Descend order by publishing year | Descend order by cited within

References

{{article.reference}}

Funding

RIGHTS & PERMISSIONS

{{article.copyrightStatement_en}}
{{article.copyrightLicense_en}}
PDF(2621 KB)

Accesses

Citation

Detail
Sections
Recommended
Copyright © Acta Electronica Sinica, All Rights Reserved.
Tel: 010-68600735　
E-mail：new@ejournal.org.cn
Powered by Beijing Magtech Co. Ltd,.
Copyright © Acta Electronica Sinica, All Rights Reserved.

/

〈 〉