A VLSI Architecture Evaluation of a Syntax Element Level Parallel Arithmetic Entropy Coder for Parallel H.264 Encoder

doi:10.3969/j.issn.0372-2112.2012.02.031

CHEN Sheng-gang;CHEN Shu-ming;GU Hui-tao;LIU Yao

Acta Electronica Sinica ›› 2012, Vol. 40 ›› Issue (2) : 400-405.

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Acta Electronica Sinica ›› 2012, Vol. 40 ›› Issue (2) : 400-405. DOI: 10.3969/j.issn.0372-2112.2012.02.031

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A VLSI Architecture Evaluation of a Syntax Element Level Parallel Arithmetic Entropy Coder for Parallel H.264 Encoder

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2012, 40(2): 400-405 https://doi.org/10.3969/j.issn.0372-2112.2012.02.031

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Received	Revised	Published
2010-05-20	2011-08-28	2012-02-25
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2012-02-25

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