A Task Scheduling Method to Increase the Reliability of the Multicore System

doi:10.3969/j.issn.0372-2112.2013.05.031

PDF(1742 KB)

ACTA ELECTRONICA SINICA ›› 2013, Vol. 41 ›› Issue (5) : 1019-1024. DOI: 10.3969/j.issn.0372-2112.2013.05.031

A Task Scheduling Method to Increase the Reliability of the Multicore System

XU Chao^1,2,3, HE Yan-xiang^1,3, CHEN Yong^1,3, LIU Jian-bo^1,3, WU Wei^1,3, LI Qing-an^1,3

Author information +

History +

Abstract

The stability and reliability of multicore systems have been gotten more attentions with the widely used in all kinds of fields.After analyzing the current reliability model for chips,a reliability evaluating model considering the temperature and workloads for the multiprocessor is proposed.Based on construction characteristic of the multiprocessor,the model hierarchically constructs the evaluating index from instruction level to the task level that enables to quantitatively evaluate the reliability of the multiprocessor.To check the effectiveness of this model,a stability-oriented task scheduling algorithm is designed to enhance the stability of multicore system.It calculates the evaluating index for each scheduling scheme and chooses the scheduling scheme with highest evaluating index to obtain the low error rate caused by multicore.According to the results of simulation experiment,we can see that this model and method are effective that have the potential to reduce 45% of the error in multicore system.

Key words

multicore system / task scheduling / stability / error evaluating model

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations

XU Chao, HE Yan-xiang, CHEN Yong, LIU Jian-bo, WU Wei, LI Qing-an. A Task Scheduling Method to Increase the Reliability of the Multicore System[J]. Acta Electronica Sinica, 2013, 41(5): 1019-1024. https://doi.org/10.3969/j.issn.0372-2112.2013.05.031

References

[1] S Rehman,M Shafique,F Kriebel,J Henkel.Reliable software for unreliable hardware:embedded code generation aiming at reliability .In Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis .Taipei,Taiwan:ACM,2011.237-246.

[2] 徐超,何炎祥,吴伟,等.基于模拟关系的编译优化实现正确性验证方法[J].电子学报,2012,40(11):2171-2176. XU Chao,HE Yan-xiang,WU Wei.Verifying implementation correctness of compiling optimization based on simulation relation[J].Acta Electronica Sinica,2012,40(11):2171-2176.(in Chinese)

[3] Maheswaran M,H J Siegel.ADynamic matching and scheduling algorithm for heterogeneous computing systems .Heterogeneous Computing Workshop .Orlando,USA:IEEE Computer Society,1998.57-69.

[4] A J Page,T J Naughton.Dynamic task scheduling using genetic algorithms for heterogeneous distributed computing .International Parallel and Distributed Processing Symposium .Denver,USA:IEEE Computer Society,2005.189-197.

[5] Y H Yang,S S Yu,X L Bin.A new dynamic scheduling algorithm for real-time heterogeneous multiprocessor systems .Proceedings of the Workshop on Intelligent Information Technology Application .Washington,USA:IEEE Computer Society,2007.112-115.

[6] Nacul A,Regazzoni F,Lajolo M.Hardware scheduling support in SMP architectures .Proceedings of the design automation and test in Europe conference .Nice,France:ACM,2007.1-6.

[7] 江维,常政威,桑楠,等.安全和能量关键的分布式协作任务调度[J].电子学报,2011,39(4):757-762. JIANG Wei,CHANG Zheng-wei,SANG Nan.Scheduling for security and energy-critical distributed collaborative tasks[J].Acta Electronica Sinica,2011,39(4):757-762.(in Chinese)

[8] J Lee,et al.Compiler approach for reducing soft errors inregister file .Conference on Languages,Compilers,and Tools for Embedded Systems .Dublin,Ireland:ACM,2009.41-49.

[9] J Yan,et al.Compiler guided register reliability improvement against soft errors .International Conference on Embedded Software .Jersey City,New Jersey,USA:IEEE Computer Society,2005.203-209.

[10] X Fu,W Zhang,T Li,J Fortes.Optimizing issue queue reliability to soft errors on simultaneous multithreaded architectures .International Conference on Parallel Processing .Portland,Oregon,USA:IEEE Computer Society,2008.190-197.

[11] V Sarkar.Optimized unrolling of nested loops[J].International Journal on Parallel Programing,2001,29(5):545-581.

[12] V Sridharan.Introducing abstraction to vulnerability analysis .Ph.D.Thesis,2010.45-55.

[13] U Schiffel,et al.Software-implemented hardware error detection:costs and gains .The Third International Conference on Dependability .Venice,Italy:IEEE Computer Society,2010.51-57.

[14] P Lokuciejewski,et al.Combining worst-case timing models,loop unrolling,and static loop analysis for WCET minimization .Euromicro Conference on Real-Time Systems(ECTRS 09) .Dublin,Ireland:IEEE Computer Society,2009.35-44.

[15] N Oh,et al.Error detection by duplicated instructions in superscalar processors[J].IEEE Transaction on Reliability,2002,51(1):63-75.

[16] J S Hu,et al.compiler-directed instruction duplication for soft error detection[J].DATE,2005,1(2):1056-1057.

[17] T Li,et al.Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin .Principles and Practice of Parallel Programming .Raleigh,North Carolina,USA:2009.65-74.

[18] A Fedorova,et al.Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler .Parallel Architectures and Compilation Techniques .Brasov,Romania:IEEE Computer Society,2007.25-38.

Funding

Key Program supported by National Natural Science Foundation of China (No.91118003); National Natural Science Foundation of China (No.61170022); Supported by Training Objects of Young Teachers in Blue Project in Jiangsu Province; Supported by Overseas Study Program for Outstanding Young and Middle-aged Teachers and Principals in Colleges and Universities of Jiangsu Province