Ternary Reversible Logic Synthesis Algorithm with Minimum Chaos Degree

XU Ming-qiang, GUAN Zhi-jin, ZHANG Hai-bao

ACTA ELECTRONICA SINICA ›› 2013, Vol. 41 ›› Issue (7) : 1352-1357.

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ACTA ELECTRONICA SINICA ›› 2013, Vol. 41 ›› Issue (7) : 1352-1357. DOI: 10.3969/j.issn.0372-2112.2013.07.017

Ternary Reversible Logic Synthesis Algorithm with Minimum Chaos Degree

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2013, 41(7): 1352-1357. https://doi.org/10.3969/j.issn.0372-2112.2013.07.017

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