Design of 12.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

PAN Min, FENG Jun, YANG Jing, YANG Lin-cheng

ACTA ELECTRONICA SINICA ›› 2014, Vol. 42 ›› Issue (8) : 1630-1635.

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ACTA ELECTRONICA SINICA ›› 2014, Vol. 42 ›› Issue (8) : 1630-1635. DOI: 10.3969/j.issn.0372-2112.2014.08.027

Design of 12.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2014, 42(8): 1630-1635. https://doi.org/10.3969/j.issn.0372-2112.2014.08.027

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