Design of 12.5Gb/s 0.18&mu;m CMOS Clock and Data Recovery Circuit

doi:10.3969/j.issn.0372-2112.2014.08.027

PDF(2688 KB)

Acta Electronica Sinica ›› 2014, Vol. 42 ›› Issue (8) : 1630-1635. DOI: 10.3969/j.issn.0372-2112.2014.08.027

Design of 12.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

{{article.zuoZhe_EN}}

Author information +

History +

HeighLight

Abstract

Key words

QR code of this article

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations

{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2014, 42(8): 1630-1635 https://doi.org/10.3969/j.issn.0372-2112.2014.08.027

References

Publishing order | Descend order by publishing year | Descend order by cited within

References

Funding

RIGHTS & PERMISSIONS

PDF(2688 KB)

Accesses

Citation

Detail

Sections

Recommended

Received	Revised	Published
2013-06-21	2013-10-23	2014-08-25
Issue Date
2014-08-25

Please choose a citation manager

Content to export