Optimization Scheme for Mid-bond Test Time on 3D-Stacked ICs

CHANG Hao, LIANG Hua-guo, JIANG Cui-yun, OUYANG Yi-ming, XU Hui

ACTA ELECTRONICA SINICA ›› 2015, Vol. 43 ›› Issue (2) : 393-398.

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ACTA ELECTRONICA SINICA ›› 2015, Vol. 43 ›› Issue (2) : 393-398. DOI: 10.3969/j.issn.0372-2112.2015.02.029

Optimization Scheme for Mid-bond Test Time on 3D-Stacked ICs

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2015, 43(2): 393-398. https://doi.org/10.3969/j.issn.0372-2112.2015.02.029

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