Reliability Calculation Method of Logical Circuit Based on Bernoulli Distribution

doi:10.3969/j.issn.0372-2112.2015.11.023

PDF(561 KB)

ACTA ELECTRONICA SINICA ›› 2015, Vol. 43 ›› Issue (11) : 2292-2297. DOI: 10.3969/j.issn.0372-2112.2015.11.023

Reliability Calculation Method of Logical Circuit Based on Bernoulli Distribution

CAI Shuo^1,2, KUANG Ji-shun¹, LIU Tie-qiao³, LING Chun-qing¹, YOU Zhi-qiang¹

Author information +

History +

Abstract

Reliability estimation of logical circuit is becoming an important feature in the design process of deep submicron and nanoscale systems.In this paper,a reliability calculation method of logical circuit based on probability statistical model is proposed.Based on this model,the correctness of every logic gate is regarded as random event and obeying Bernoulli distribution.Meanwhile,simulation experimental results are given to analyze the logical masking properties of the circuit when only one gate set as faulty.To validate the proposed methodology we have studied the reliability range of ISCAS'85 and ISCAS'89 benchmark circuits.Theoretical analysis and experimental results show our method is accurate and efficient.

Key words

soft error / reliability / probabilistic statistical model / logic mask / Bernoulli distribution

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations

CAI Shuo, KUANG Ji-shun, LIU Tie-qiao, LING Chun-qing, YOU Zhi-qiang. Reliability Calculation Method of Logical Circuit Based on Bernoulli Distribution[J]. Acta Electronica Sinica, 2015, 43(11): 2292-2297. https://doi.org/10.3969/j.issn.0372-2112.2015.11.023

References

[1] Krishnaswamy S,Viamontes G F,Markov I L,et al.Accurate reliability evaluation and enhancement via probabilistic transfer matrices[A]. Proceedings of Design,Automation and Test in Europe Conference and Exhibition,Munich[C]. New York:ACM Society,2005.282-287.
[2] 王真,江建慧,沈君华,等.基于概率转移矩阵的电路可靠性并行计算方法[J]. 小型微型计算机系统,2008,29(2):357-360. Wang Z,et al.Parallelprocessing of the probabilistic transfer matrix based circuits reliability calculation[J]. Journal of Chinese Computer Systems,2008,29(2):357-360.(in Chinese)
[3] 王真,江建慧.基于概率转移矩阵的串行电路可靠度计算方法[J]. 电子学报,2009,37(2):241-247. Wang Z,Jiang J H.A serial method of circuit reliability calculation based on probabilistic transfer matrix[J]. Acta Electronica Sinica,2009,37(2):241-247.(in Chinese)
[4] Jie Xiao,Jianhui Jiang,Xuguang Zhu,et al.A method of gate-level circuit reliability estimation based on iterative PTM model[A]. Proceedings of the 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing[C]. Pasadena,California,USA:IEEE Computer Society,2011.276-277.
[5] 肖杰,江建慧,朱旭光.一种基于迭代PTM模型的电路可靠性评估方法[J]. 计算机学报,2014,37(7):1508-1520. Xiao J,Jiang J H,et al.Amethod of circuit reliability estimation based on iterative PTM model[J]. Chinese Journal of Computers,2014,37(7):1508-1520.(in Chinese)
[6] Franco DT,Vasconcelos MC,et al.Reliability analysis of logic circuits based on signal probability[A]. 15^th IEEE International Conference on Electronics,Circuits and Systems[C]. St Julien's,Malta:IEEE Computer Society,2008.670-673.
[7] Franco DT,Vasconcelos MC,Naviner L,et al.Reliability of logic circuits under multiple simultaneous faults[A]. 51^st Midwest Symposium on Circuits and Systems[C]. Knoxville,TN:IEEE Computer Society,2008.265-268.
[8] J Torras Flaquer,J M Daveau,et al.Fast reliability analysis of combinatorial logic circuits using conditional probabilities[J]. Microelectronics Reliability,2010,50(9):1215-1218.
[9] 蔡烁,邝继顺,刘铁桥,等.一种高效的门级电路可靠度估算方法[J]. 电子与信息学报,2013,35(5):1262-1266. Cai S,Kuang J S,et al.An efficient reliability estimation method for gate-level circuit[J]. Journal of Electronics & Information Technology,2013,35(5):1262-1266.(in Chinese)
[10] Singh N S S,Hamid N H,Asirvadam V S,et al.Evaluation of circuit reliability based on distribution of different signal input patterns[A]. 8^th IEEE International Colloquium on Signal Processing and Its Applications[C]. Melaka,Malaysia:IEEE Computer Society,2012:5-9.
[11] Singh N S S,Hamid N H,Asirvadam V S,et al.Sensitivity analysis of probability transfer matrix(PTM) on same functionality circuit architectures[A]. 8^th IEEE International Colloquium on Signal Processing and Its Applications[C]. Melaka,Malaysia:IEEE Computer Society,2012:250-254.
[12] 欧阳城添,江建慧.基于概率转移矩阵的时序电路可靠度估计方法[J]. 电子学报,2013,41(1):171-177. OuYang C T,Jiang J H.Reliability estimation of sequential circuit based on probabilistic transfer matrices[J]. Acta Electronica Sinica,2013,41(1):171-177.(in Chinese)
[13] Seyyed Mahdavi S J,Mohammadi K.SCRAP:Sequential circuits reliability analysis program[J]. Microelectronics Reliability,2009,49(8):924-933.
[14] K Lingasubramanian,S Bhanja.An error model to study the behavior of transient errors in sequential circuits[A]. Proc Of 22^nd International Conference on VLSI Design[C]. New Delhi,India:IEEE Computer Society,2009.485-490.

Funding

National Natural Science Foundation of China (No.61303042, No.60773207, No.61472123); Research Fund of Education Department of Hunan Province (No.14C0028)