Dynamic Bottleneck Analysis for Semiconductor Wafer Fabrication System Based on Growing and Pruning Neural Networks

doi:10.3969/j.issn.0372-2112.2016.07.017

CAO Zheng-cai, QIU Ming-hui, LIU Min

ACTA ELECTRONICA SINICA ›› 2016, Vol. 44 ›› Issue (7) : 1636-1642.

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ACTA ELECTRONICA SINICA ›› 2016, Vol. 44 ›› Issue (7) : 1636-1642. DOI: 10.3969/j.issn.0372-2112.2016.07.017

Dynamic Bottleneck Analysis for Semiconductor Wafer Fabrication System Based on Growing and Pruning Neural Networks

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2016, 44(7): 1636-1642. https://doi.org/10.3969/j.issn.0372-2112.2016.07.017

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Received	Revised	Published
2014-02-27	2014-07-07	2016-07-25
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2016-07-25

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