Design of a Low Jitter Delay Locked Loop for TDC

doi:10.3969/j.issn.0372-2112.2017.02.026

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Acta Electronica Sinica ›› 2017, Vol. 45 ›› Issue (2) : 452-458. DOI: 10.3969/j.issn.0372-2112.2017.02.026

Design of a Low Jitter Delay Locked Loop for TDC

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2017, 45(2): 452-458 https://doi.org/10.3969/j.issn.0372-2112.2017.02.026

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Received	Revised	Published
2015-10-13	2016-03-08	2017-02-25
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2017-02-25

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