A Novel Reconfigurable Rotation-Permutation Unit Research and Implementation

doi:10.3969/j.issn.0372-2112.2017.05.001

PDF(1706 KB)

ACTA ELECTRONICA SINICA ›› 2017, Vol. 45 ›› Issue (5) : 1025-1034. DOI: 10.3969/j.issn.0372-2112.2017.05.001

A Novel Reconfigurable Rotation-Permutation Unit Research and Implementation

MA Chao¹, LI Wei², DAI Zi-bin¹, FENG Xiao¹

Author information +

History +

Abstract

In this paper,a high speed reconfigurable control bits generation algorithm for rotation shift operations is proposed.The algorithm utilizes self-reconfigurable characteristics of the Inverse Butterfly/Butterfly network,and it is highly parallelized and low-cost.Moreover,it also integrates more than 10 kinds of rotation shift operations together,including rotation shift,bidirectional rotation shift,and sub-word rotation shift based on a bit width of 2ⁱ(i=1,2,…).Following this,a new high-speed reconfigurable rotation-permutation unit(HRRU)is developed and synthesized in SMIC 65-nm process.The results show that the proposed unit only containing rotation shift operations,enhances the frequency by 6.4%~12% and reduces the area by 22%~30%,compared with previously proposed solutions.When achieving a variety of rotation shift operations,the frequency of our unit decreases by 8.4%.But it can support twice operations as many as previous designs.

Key words

Inverse Butterfly/Butterfly Network / rotation algorithm / reconfigurable / sub-word rotation operations

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations

MA Chao, LI Wei, DAI Zi-bin, FENG Xiao. A Novel Reconfigurable Rotation-Permutation Unit Research and Implementation[J]. Acta Electronica Sinica, 2017, 45(5): 1025-1034. https://doi.org/10.3969/j.issn.0372-2112.2017.05.001

References

[1] Trived P,Tripathi R P.Design and analysis of 16 bit RISC processor using low power pipelining[A].IEEE International Conference on Computing,Communication & Automation(ICCCA)[C].India:IEEE,2015.1294-1297.
[2] Khan L.Designing of low power high speed 32-bit barrel shifter for ARM7 processor[J].International Journal of Advanced Research in Computer Science,2013,4(3):108-113.
[3] Hosseininia N,Boroumand S,Haghparast M.Novel nanometric reversible low power bidirectional universal logarithmic barrel shifter with overflow and zero flags[J].Journal of Circuits System and Computers,2015,24(04):1-14.
[4] Shan W,Chen X,Lu Y C,et al.A novel combinatorics-based reconfigurable bit permutation network and its circuit implementation[J].Chinese Journal of Electronics,2015,24(3):513-517.
[5] Ao T,He Z,Dai K.Low-cost bit permutation circuit with concise configuration rule[A].Proceedings of the International MultiConference of Engineers and Computer Scientists[C].Hong Kong:International Association of Engineers,2015.158-160.
[6] Kolay S,Khurana S.PERMS:a bit permutation instruction for accelerating software cryptography[A].16th Euromicro Conference on Digital System Design[C].Spain:IEEE,2013:963-968.
[7] Sayilar G,Chiou D.Cryptoraptor:high throughput reconfigurable cryptographic processor[A].IEEE International Conference on Computer-Aided Design(ICCAD)[C].San Jose:IEEE,2014.155-161.
[8] Shan W.,Fu X,Xu Z.A secure reconfigurable crypto IC with countermeasures against SPA,DPA and EMA[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2015,34(7):1201-1205.
[9] Hilewitz Y,Lee R B.A new basis for shifters in general-purpose processors for existing and advanced bit manipulations[J].IEEE Transactions on Computers,2009,58(8):1035-1048.
[10] Hilewitz Y,Lee R B.Fast bit gather,bit scatter and bit permutation instructions for commodity microprocessors[J].Journal of Signal Processing Systems,2008,53(1-2):145-169.
[11] Hilewitz Y,Shi Z J,Lee R B.Comparing fast implementations of bit permutation instructions[A].38th IEEE Annual Asilomar Conference on Signals,Systems,and Computers[C].United State:IEEE,2004.1856-1863.
[12] Intel Corporation,Intel Itanium Architecture Software Developer's Manual[S].2006.
[13] Shi Z,Yang X,Lee R B.Arbitrary bit permutations in one or Two cycles[A].14th IEEE International Conference on Application-Specific Systems,Architectures and Processors[C].Netherlands:IEEE,2003.237-237.
[14] Chang Zhongxiang,Hu Jinshan,Ma Chao.Research on shifter based on ibutterfly network[A].17th China Computer Federation[C].Xi Ning,China:Springer-Verlag,2013.92-100.
[15] Nassimi D,Sahni S A.Self_routing benes network and parallel permutation algorithm[J].IEEE Transaction on Computers,1981,30(5):332-340.
[16] 戴浩,沈孝钧.在7级混洗交换网络中实现16×16的可重排性[J].电子学报,2007,35(10):1875-1885. Dai Hao,Shen Xiaojun.Rearrageability of the 7-stage 16×16 shuffe exchange network[J].Acta Electronica Sinica,2007,35(10):1875-1885.(in Chinese)
[17] Vidhya S P,Venkatesulu M.A block cipher based on boolean matrices using bit level operations[A].13th IEEE International Conference on Computer and Information Science(ICIS)[C].Tai Yuan:IEEE,2014.59-63.
[18] Bansod G,Raval N,Pisharoty N.Implementation of a new lightweight encryption design for embedded security[J].IEEE Transactions on Information Forensics and Security,2015,10(1):142-151.
[19] Intel Corporation.Haswell Intel Architecture Software Developer's Manual[S].2014.
[20] Rajkumar S,Goyal N K.Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection Networks[J].Journal of Supercomputing,2014,69(1):468-491.
[21] Semiconductor Manufacturing International Corporation.SMIC 55nm Logic Process Standard Cell Library Databook[S].2012.