Reconfigurable Asymmetrical Multi-core Architecture for Block Cipher

doi:10.3969/j.issn.0372-2112.2017.06.005

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ACTA ELECTRONICA SINICA ›› 2017, Vol. 45 ›› Issue (6) : 1311-1320. DOI: 10.3969/j.issn.0372-2112.2017.06.005

Reconfigurable Asymmetrical Multi-core Architecture for Block Cipher

FENG Xiao¹, LI Wei², DAI Zi-bin¹, MA Chao¹, LI Gong-li¹

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Abstract

Among the existing reconfigurable block cipher hardware structures,the special instruction processor does not achieve high throughput rate,while resource utilization of the reconfigurable block cipher processing array is low and mapping process is very complicated.Therefore,the reconfigurable asymmetrical multi-core architecture (RAMCA) for block cipher was designed.Mapping processes of typical structures,which were SP (AES-128),Feistel (SMS4),L-M (IDEA) and MISTY (KASUMI),was analyzed.Hardware implementation was designed and synthesized in a 65nm CMOS process.The experimental area is about 1.13sq mm while frequency reaches 1GHz.After the influence of the process is eliminated,the performance of RAMCA is higher than that of other special instruction processors and most of the reconfigurable block cipher processing arrays,such as Celator,RCPA,BCORE,etc.

Key words

block cipher / heterogeneous multi-core / reconfigurable / parallel processing / cipher processor

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FENG Xiao, LI Wei, DAI Zi-bin, MA Chao, LI Gong-li. Reconfigurable Asymmetrical Multi-core Architecture for Block Cipher[J]. Acta Electronica Sinica, 2017, 45(6): 1311-1320. https://doi.org/10.3969/j.issn.0372-2112.2017.06.005

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