Design and Optimization of FPGA Clock Network Based on Parameterized Model

doi:10.3969/j.issn.0372-2112.2017.07.019

YU Le, CHEN Yan, LI Yang-yang, WU Chao, WANG Yao, SU Tong, XIE Yuan-lu

Acta Electronica Sinica ›› 2017, Vol. 45 ›› Issue (7) : 1686-1694.

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Acta Electronica Sinica ›› 2017, Vol. 45 ›› Issue (7) : 1686-1694. DOI: 10.3969/j.issn.0372-2112.2017.07.019

Design and Optimization of FPGA Clock Network Based on Parameterized Model

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2017, 45(7): 1686-1694 https://doi.org/10.3969/j.issn.0372-2112.2017.07.019

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Received	Revised	Published
2016-06-13	2016-12-09	2017-07-25
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2017-07-25

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