Four Dimensions Parallel Processing Architecture for Block Cipher

WANG Shou-cheng, LI Gong-li, YAN Ying-jian, XU Jin-hui

Acta Electronica Sinica ›› 2017, Vol. 45 ›› Issue (10) : 2457-2463.

PDF(5569 KB)
CIE Homepage  |  Join CIE  |  Login CIE  |  中文 
PDF(5569 KB)
Acta Electronica Sinica ›› 2017, Vol. 45 ›› Issue (10) : 2457-2463. DOI: 10.3969/j.issn.0372-2112.2017.10.021

Four Dimensions Parallel Processing Architecture for Block Cipher

    {{javascript:window.custom_author_en_index=0;}}
  • {{article.zuoZhe_EN}}
Author information +

HeighLight

{{article.keyPoints_en}}

Abstract

{{article.zhaiyao_en}}

Key words

QR code of this article

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations
{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2017, 45(10): 2457-2463 https://doi.org/10.3969/j.issn.0372-2112.2017.10.021

References

Publishing order | Descend order by publishing year | Descend order by cited within

References

{{article.reference}}

Funding

RIGHTS & PERMISSIONS

{{article.copyrightStatement_en}}
{{article.copyrightLicense_en}}
PDF(5569 KB)

Accesses

Citation

Detail
Sections
Recommended
Copyright © Acta Electronica Sinica, All Rights Reserved.
Tel: 010-68600735　
E-mail：new@ejournal.org.cn
Powered by Beijing Magtech Co. Ltd,.
Copyright © Acta Electronica Sinica, All Rights Reserved.

/

〈 〉