High-Performance Parallel Fully Redundant Decimal Multiplier

doi:10.3969/j.issn.0372-2112.2018.06.036

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ACTA ELECTRONICA SINICA ›› 2018, Vol. 46 ›› Issue (6) : 1519-1523. DOI: 10.3969/j.issn.0372-2112.2018.06.036

High-Performance Parallel Fully Redundant Decimal Multiplier

ZHANG Liu, CUI Xiao-ping, DONG Wen-wen

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Abstract

High-performance decimal hardware arithmetic is now a high demand due to the requirement for accurate computation in fields like commercial computing and financial analysis.The performance of fully redundant decimal multiplier is limited because the circuit for fully redundant adder is complex.A modified fully redundant adder based on overloaded decimal digit set (ODDS) and a new decimal reduction tree based on fully redundant ODDS adders are proposed.The signed-digit radix-10 recoding and redundant binary coded decimal (BCD) codes are used for fast partial product generation.A recoding conversion circuit is proposed to generate BCD-8421 product fast.Comparison shows that the delay and area of the proposed decimal multiplier are small.

Key words

multiplier / decimal arithmetic / BCD coding / redundant coding / fully redundant adder / recoding conversion

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ZHANG Liu, CUI Xiao-ping, DONG Wen-wen. High-Performance Parallel Fully Redundant Decimal Multiplier[J]. Acta Electronica Sinica, 2018, 46(6): 1519-1523. https://doi.org/10.3969/j.issn.0372-2112.2018.06.036

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Funding

National Natural Science Foundation of China (No.61404087); Aeronautical Science Foundation of China, ASFC (Key Laboratory Fund) (No.20152052025); Open Fund of Postgraduate Innovation Base (laboratory) of Nanjing University of Aeronautics and Astronautics (No.kfjj20160407); Fundamental Research Funds for the Central Universities (No.NS2015045)