Design of a Low Jitter Phase Locked Loop for Array TDC

WU Jin, SUN Ya-wei, PENG Jie, ZHENG Li-xia, LUO Mu-chang, SUN Wei-feng

ACTA ELECTRONICA SINICA ›› 2020, Vol. 48 ›› Issue (9) : 1703-1710.

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ACTA ELECTRONICA SINICA ›› 2020, Vol. 48 ›› Issue (9) : 1703-1710. DOI: 10.3969/j.issn.0372-2112.2020.09.006

Design of a Low Jitter Phase Locked Loop for Array TDC

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2020, 48(9): 1703-1710. https://doi.org/10.3969/j.issn.0372-2112.2020.09.006

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