A Virtual 3-D Multipole Accelerated Extractor for VLSI Parasitic Interconnect Capacitance

A Virtual 3-D Multipole Accelerated Extractor for VLSI Parasitic Interconnect Capacitance

YANG Zhao-zhi;WANG Ze-yi;FANG Shu-zhou

ACTA ELECTRONICA SINICA ›› 2000, Vol. 28 ›› Issue (11) : 129-131.

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PDF(160 KB)

ACTA ELECTRONICA SINICA ›› 2000, Vol. 28 ›› Issue (11) : 129-131.

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A Virtual 3-D Multipole Accelerated Extractor for VLSI Parasitic Interconnect Capacitance

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2000, 28(11): 129-131.

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