Numerical Simulation of Time Delay and Cross-talk Noise for the Interconnect in VLSI Circuits

RUAN Gang;XIAO Xia;SONG Ren-ru;Reinhard Streiter;Thomas Otto;Thomas Gessner

ACTA ELECTRONICA SINICA ›› 2000, Vol. 28 ›› Issue (5) : 142-144.

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ACTA ELECTRONICA SINICA ›› 2000, Vol. 28 ›› Issue (5) : 142-144.
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Numerical Simulation of Time Delay and Cross-talk Noise for the Interconnect in VLSI Circuits

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2000, 28(5): 142-144.

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