VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture

ZHANG Guang-lie;ZHENG Nan-ning;WU Yong;ZHANG Xia

ACTA ELECTRONICA SINICA ›› 2002, Vol. 30 ›› Issue (7) : 945-948.

PDF(171 KB)
CIE Homepage  |  Join CIE  |  Login CIE  |  中文 
PDF(171 KB)
ACTA ELECTRONICA SINICA ›› 2002, Vol. 30 ›› Issue (7) : 945-948.
论文

VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture

    {{javascript:window.custom_author_en_index=0;}}
  • {{article.zuoZhe_EN}}
Author information +

HeighLight

{{article.keyPoints_en}}

Abstract

{{article.zhaiyao_en}}

Key words

QR code of this article

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations
{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2002, 30(7): 945-948.

References

Publishing order | Descend order by publishing year | Descend order by cited within

References

{{article.reference}}

Funding

RIGHTS & PERMISSIONS

{{article.copyrightStatement_en}}
{{article.copyrightLicense_en}}
PDF(171 KB)

Accesses

Citation

Detail
Sections
Recommended
Copyright © ACTA ELECTRONICA SINICA, All Rights Reserved.
E-mail：new@ejournal.org.cn
Powered by Beijing Magtech Co. Ltd,.
Copyright © ACTA ELECTRONICA SINICA, All Rights Reserved.

/

〈 〉