Design and Implementation of a Multi-Channel High Speed HDLC Data Processor

Design and Implementation of a Multi-Channel High Speed HDLC Data Processor

LU Yuan-lin;QIAO Lu-feng;WANG Zhi-gong

ACTA ELECTRONICA SINICA ›› 2003, Vol. 31 ›› Issue (11) : 1630-1633.

PDF(242 KB)

PDF(242 KB)

ACTA ELECTRONICA SINICA ›› 2003, Vol. 31 ›› Issue (11) : 1630-1633.

论文

Design and Implementation of a Multi-Channel High Speed HDLC Data Processor

{{article.zuoZhe_EN}}

Author information +

History +

HeighLight

{{article.keyPoints_en}}

Abstract

{{article.zhaiyao_en}}

Key words

QR code of this article

Cite this article

Download Citations

{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2003, 31(11): 1630-1633.

References

Publishing order | Descend order by publishing year | Descend order by cited within

References

{{article.reference}}

Funding

RIGHTS & PERMISSIONS

{{article.copyrightStatement_en}}

{{article.copyrightLicense_en}}

PDF(242 KB)

Accesses

Citation

Detail

Sections

Recommended

/

〈

〉