Study on a Novel Probability Decoder Implemented by Analog LSI

YANG Shu-hui;QIU Yu-lin

ACTA ELECTRONICA SINICA ›› 2004, Vol. 32 ›› Issue (2) : 236-240.

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ACTA ELECTRONICA SINICA ›› 2004, Vol. 32 ›› Issue (2) : 236-240.
论文

Study on a Novel Probability Decoder Implemented by Analog LSI

  • YANG Shu-hui, QIU Yu-lin
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Abstract

Using the subthreshold MOS transistors,a low power current-mode multiplier is given in the paper.By adopting the multiplier as the kernel circuit,some modules used to compute the probability are designed.On the bases of these modules and the MAP algorithm,a soft-decision probability decoder of the (5,2,3) trellis code is implemented,and a novel pipelining serial input interface for the decoder is proposed.To verify the performance,the decoder is simulated with the model of standard 0.6μm CMOS process.

Key words

analog multiplier / maximum a posteriori probability(MAP)algorithm / soft-decision decoding / trellis code / probability decoder

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YANG Shu-hui;QIU Yu-lin. Study on a Novel Probability Decoder Implemented by Analog LSI[J]. Acta Electronica Sinica, 2004, 32(2): 236-240.
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