The Buffer Structure and Scheduling Algorithm for Maintaining Packet Order in the Parallel Switch

LAN Ju-long, DONG Yu-guo, CHEN Yue, WEN Jian-hua

ACTA ELECTRONICA SINICA ›› 2004, Vol. 32 ›› Issue (S1) : 35-38.

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ACTA ELECTRONICA SINICA ›› 2004, Vol. 32 ›› Issue (S1) : 35-38.

The Buffer Structure and Scheduling Algorithm for Maintaining Packet Order in the Parallel Switch

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2004, 32(S1): 35-38.

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