Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM

Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM

WANG Peng-jun, YU Jun-jun

ACTA ELECTRONICA SINICA ›› 2006, Vol. 34 ›› Issue (2) : 301-305.

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PDF(264 KB)

ACTA ELECTRONICA SINICA ›› 2006, Vol. 34 ›› Issue (2) : 301-305.

Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2006, 34(2): 301-305.

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