State of the Art on Study of Parametric Yield and Its Optimization for VLSI

HAO Yue; JING Ming-e; MA Pei-jun

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State of the Art on Study of Parametric Yield and Its Optimization for VLSI

更新时间：2025-07-16

- State of the Art on Study of Parametric Yield and Its Optimization for VLSI
- Acta Electronica Sinica Vol. 31, Issue S1, Pages: 1971-1974(2003)
- 作者机构：
  
  西安电子科技大学微电子研究所,陕西,西安,710071
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN405
- Published Online：25 December 2003，
  
  Published：2003
- 稿件说明：
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HAO Yue, JING Ming-e, MA Pei-jun. State of the Art on Study of Parametric Yield and Its Optimization for VLSI[J]. Acta Electronica Sinica, 2003, 31(S1): 1971-1974.
DOI：

HAO Yue, JING Ming-e, MA Pei-jun. State of the Art on Study of Parametric Yield and Its Optimization for VLSI[J]. Acta Electronica Sinica, 2003, 31(S1): 1971-1974. DOI：

摘要

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素

随着集成电路(IC)进入超深亚微米发展阶段

芯片工作速度不断增加

集成度和复杂度提高

而工艺容差减小的速度跟不上这种变化

因此参数成品率的研究越来越重要.本文系统地讨论了参数成品率的模型和设计技术研究进展

分析不同技术的特点和局限性.最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向.

Abstract

Parametric Yield of VLSI is an important factor related with manufactory cost and circuit performance.With development of deep sub-micron IC technologies

chips have led to a large increase in system complexity and the number of devices per die as well as the switching speeds.These advances have been accompanied by parametric yield loss due to the fluctuations in the manufactory process.Firstly

models and design technology of parametric yield is systematically discussed in this paper.Their advantages and disadvantages are discussed in details.Finally

the main problems and developing direction of parametric yield design and enhancement in very deep sub-micron regime are given.

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A Multi-objective Optimization Framework for Robust IC Parametric Yield Predication Under Process Variations

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