Novel CMOS Ternary Edge-triggered Flip-flop

WU Xun-wei; WEI Jian; WANG Peng-Jun

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Novel CMOS Ternary Edge-triggered Flip-flop

更新时间：2025-07-16

- Novel CMOS Ternary Edge-triggered Flip-flop
- Acta Electronica Sinica Vol. 28, Issue 9, Pages: 126-127(2000)
- 作者机构：
  
  1. 宁波大学电路与系统研究所,宁波,315211
  2. 浙江大学信电系,杭州,310027
  3. 宁波大学电路与系统研究所宁波,315211
  4. 浙江大学信电系杭州,310027
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN432TP343
- Published：2000
- 稿件说明：
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WU Xun-wei, WEI Jian, WANG Peng-Jun. Novel CMOS Ternary Edge-triggered Flip-flop[J]. Acta Electronica Sinica, 2000, 28(9): 126-127.
DOI：

WU Xun-wei, WEI Jian, WANG Peng-Jun. Novel CMOS Ternary Edge-triggered Flip-flop[J]. Acta Electronica Sinica, 2000, 28(9): 126-127. DOI：

摘要

本文利用时钟信号的竞争冒险现象

提出了CMOS时钟信号竞争型三值

型边沿触发器的逻辑设计.通过PSPICE程序模拟

证实了该设计具有正确的逻辑功能

而且与传统的三值

型维持阻塞触发器相比

它具有更简单的结构和更低的功耗.

Abstract

The narrow pulse produced by the race-hazard of clock is used to control the ternary latch

so as to meet the 'non-transparent’ demand.Based on it

a CMOS

-type ternary edge-triggered flip-flop is proposed.This design is proved to have an exact logic function by PSPICE simulation

and it has a simple construction and lower power dissipation at the same time.

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Related Author

LI Kun-peng

WANG Peng-jun

WU Xun-wei

HANG Guo-qiang

SHI Yin

WANG Ping

ZHANG Xiao-lin

CAO Xiang-rong

Related Institution

Institute of Circuits and Systems, Ningbo University

宁波大学电路与系统研究所浙江宁波

浙江大学信息与电子工程学系浙江杭州

浙江大学信息与电子工程学系

Institute of Semiconductors,Chinese Academy of Science,P.O.Box 912

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