Simulation of Electrical Performance for High-Speed Dual-Coplanar PCB

CAI Xing-jian; CAO Yi; MAO Jun-fa; LI Zheng-fan

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Simulation of Electrical Performance for High-Speed Dual-Coplanar PCB

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- Simulation of Electrical Performance for High-Speed Dual-Coplanar PCB
- Acta Electronica Sinica Vol. 29, Issue 2, Pages: 287-288(2001)
- 作者机构：
  
  上海交通大学电子工程系,上海,200030
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN41
- Published：2001
- 稿件说明：
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CAI Xing-jian, CAO Yi, MAO Jun-fa, et al. Simulation of Electrical Performance for High-Speed Dual-Coplanar PCB[J]. Acta Electronica Sinica, 2001, 29(2): 287-288.
DOI：

CAI Xing-jian, CAO Yi, MAO Jun-fa, et al. Simulation of Electrical Performance for High-Speed Dual-Coplanar PCB[J]. Acta Electronica Sinica, 2001, 29(2): 287-288. DOI：

摘要

为了适应高速双面共面印刷电路板的不规则布线结构

本文采用三维电磁参数提取的部分元等效电路方法对任意形状接地/馈电板进行自动分割及单元建模

然后对包括I/O缓冲器在内的非线性电路进行时域信号响应分析.高速双面共面结构印刷电路板电特性的仿真与实际测试结果吻合较好

表明了方法的有效性.

Abstract

In order to accommodate to the irregular fabrication configuration

the 3D electromagnetic parameters extraction method of partial element equivalent circuit (PEEC) technology is used to model the cells of automatically partitioned ground/feeding plane with arbitrary shape.Then the response analysis in the time domain for the nonlinear circuit including I/O buffers is performed.The simulation result for a high-speed dual-coplanar PCB well fits the measured one

which indicates the validity of the proposed method.

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