您当前的位置:
首页 >
文章列表页 >
New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Image and Its Low-Power VLSI Architecture
更新时间:2025-07-16
    • New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Image and Its Low-Power VLSI Architecture

    • Acta Electronica Sinica   Vol. 29, Issue 6, Pages: 860-864(2001)
    • CLC: TN912
    • Published:2001

    移动端阅览

  • ZHANG Wu-jian, QIU Xiao-hai, ZHOU Run-de, et al. New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Image and Its Low-Power VLSI Architecture[J]. Acta Electronica Sinica, 2001, 29(6): 860-864. DOI:

  •  
  •  
icon
试读结束,您可以激活您的VIP账号继续阅读。
去激活 >
icon
试读结束,您可以通过登录账户,到个人中心,购买VIP会员阅读全文。
已是VIP会员?
去登录 >

0

Views

826

下载量

2

CSCD

Alert me when the article has been cited
提交
Tools
Download
Export Citation
Share
Add to favorites
Add to my album

Related Articles

Frame-Level Pipelined Array Architecture for Motion Estimation
A Programmable Heterogeneous Chip Designed for Video Bridging
Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors
A Sub-1 V 10 bit SAR ADC Robust Against Process-Voltage-Temperature Variation
Low Power Test Data Compression Technique Based on Reconfigurable MUXs Network

Related Author

HE Wei-feng
MAO Zhi-gang
WANG Pan-feng
CAI Yi-ci
WEI Cong
HUANG Li-jie
HU Wei
WEI Rong-shan

Related Institution

Department of Microelectronics Science and Technology,Harbin Institute of Technology
Hercules Microelectronics, Co., Ltd.
Department of Computer Science and Technology, Tsinghua University
School of Physics and Information Engineering, Fuzhou University
Shaanxi Provincial Research Center for Telecommunication ASIC Design, Xi’an University of Posts and Telecommunications
0