Constrained Via Minimization with Practical Considerations for Different-Styled Multi-Layer Routing

MA Qi; YAN Xiao-lang

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Constrained Via Minimization with Practical Considerations for Different-Styled Multi-Layer Routing

更新时间：2025-07-16

- Constrained Via Minimization with Practical Considerations for Different-Styled Multi-Layer Routing
- Acta Electronica Sinica Vol. 29, Issue 8, Pages: 1086-1089(2001)
- 作者机构：
  
  1. 杭州电子工业学院CAD研究所,浙江,杭州,310037
  2. 浙江大学电气工程学院,浙江,杭州,310027
  3. 杭州电子工业学院CAD研究所浙江杭州,310037
  4. 浙江大学电气工程学院浙江杭州,310027
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN402
- Published：2001
- 稿件说明：
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MA Qi, YAN Xiao-lang. Constrained Via Minimization with Practical Considerations for Different-Styled Multi-Layer Routing[J]. Acta Electronica Sinica, 2001, 29(8): 1086-1089.
DOI：

MA Qi, YAN Xiao-lang. Constrained Via Minimization with Practical Considerations for Different-Styled Multi-Layer Routing[J]. Acta Electronica Sinica, 2001, 29(8): 1086-1089. DOI：

摘要

本文分析了常用的VLSI多层布线图模型线段－相交图SCG的局限性

提出了对SCG模型的修正

并基于该模型用模拟退火算法来解决通孔最少化问题

算法可以处理严格和非严格分层的布线

并考虑了许多物理约束的处理方法.实验证明算法可以较大程度地减少通孔.

Abstract

The weakness of the commonly-used Segment-Crossing Graph (SCG) model for VLSI multi-layer routing is first discussed

then a Modified Segment-Crossing Graph model is preserted

and finally a modified simulated annealing approach for constrained via minimization problem on the basis of this model is given.In the algorithm

many physical constraints are taken into consideration

and both restricted and non-restricted layer model routing can be treated.The experimental results prove the number of vias can be reduced largely.

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