您当前的位置:
首页 >
文章列表页 >
A Fast Method for 3-D VLSI Interconnect Capacitance Extraction: Quasi-Multiple Medium Method
更新时间:2025-07-16
    • A Fast Method for 3-D VLSI Interconnect Capacitance Extraction: Quasi-Multiple Medium Method

    • Acta Electronica Sinica   Vol. 29, Issue 11, Pages: 1526-1529(2001)
    • CLC: O241
    • Published:2001

    移动端阅览

  • YU Wen-jian, WANG Ze-yi, HOU Jin-song. A Fast Method for 3-D VLSI Interconnect Capacitance Extraction: Quasi-Multiple Medium Method[J]. Acta Electronica Sinica, 2001, 29(11): 1526-1529. DOI:

  •  
  •  
icon
试读结束,您可以激活您的VIP账号继续阅读。
去激活 >
icon
试读结束,您可以通过登录账户,到个人中心,购买VIP会员阅读全文。
已是VIP会员?
去登录 >

0

Views

854

下载量

0

CSCD

Alert me when the article has been cited
提交
Tools
Download
Export Citation
Share
Add to favorites
Add to my album

Related Articles

Optimization and Capacitance Characteristics of 1 500 V Super Junction Power MOS Devices
Single-Node SOR Method for Statistic Analysis of Power/Ground Networks
Efficient Extraction of the Frequency-Dependent K Element and Resistance of VLSI Interconnects
New Rate Control Algorithm Truncating Real Time for JPEG2000 and Its VLSI Architecture Design

Related Author

HONG Xian-long
WANG Ze-yi
GU Jiang-chun
CHONG Yi-ning
LI Jue
QIAO Ming
Xu Xuan-chuan
Pan Yue-dou

Related Institution

Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China
Guangdong Institute of Electronic Information Engineering, University of Electronic Science and Technology of China
National Key Laboratory of Electronic Thin Film and Integrated Devices, University of Electronic Science and Technology of China
College of Information Science and TechnologyBeijing Science and Technology UniversityBeijing 100082China
College of Information Science and TechnologyBeijing Normal UniversityBeijing 100875China
0