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北京大学微电子学研究所,北京,100871
Published:2002
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XU Xiao-yan, TAN Jing-rong, GAO Wen-yu, et al. Electrical Characteristics of 3.4nm Gate Oxide[J]. Acta Electronica Sinica, 2002, 30(2): 269-270.
用LOCOS工艺制备出栅介质厚度为3.4nm的MOS电容样品
通过对样品进行
I-V
特性和恒流应力下
V-t
特性的测试
分析用氮气稀释氧化法制备的栅介质的性能
同时考察了硼扩散对栅介质性能的影响.实验结果表明
制备出的3.4nm SiO
2
栅介质的平均击穿场强为16.7MV/cm
在恒流应力下发生软击穿
平均击穿电荷为2.7C/cm
2
.栅介质厚度相同的情况下
P
+
栅样品的击穿场强和软击穿电荷都低于N
+
栅样品.
MOS capacitors with 3.4nm gate oxide layer were manufactured in this experiment.By measuring current voltage characteristic and evolution of the gate voltage during constant current stress of the capacitors
the electrical characteristics of the gate oxide have been studied.In addition
the effect of boron penetration on gate oxide was investigated.The experimental results showed that the average breakdown field of the 3.4nm gate oxide was 16.7MV/cm.Under constant current stress
soft breakdown occured and the average charge-to-breakdown was 2.7C/cm
2.For p
+
polysilicon gate MOS capacitor
breakdown field and charge-to-breakdown of gate oxide were all decreased because of boron penetration.
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