Presents a high-speed programmable logic cell for datapath

whose architecture consists of enhanced multiplexer.When the cell is configured for XOR-XNOR-MUX scheme

it can achieve the functions such as one bit full adder and base multiplier cell and so on for datapath application.It is also configured for all 3-input logic and some logic between 4 and 7 input

and used for general combinational logic.The cell is only made up of three 2:1 MUX and two enhanced 2:1 MUX inverted by programming

achieves fast speed and costs little chip area.The advantages of its speed and area are proved by simulation analysis with HSPICE.The larger-propagating delay is less than 0.6ns and the carry-chain delay is less than 0.1ns under 5V

0.6μs CMOS process.