A novel CMOS ternary D-type edge-triggered flip-flop using a single latch is presented.In the proposed circuit

data are sampled into the latch during a short transparency period for rising edge of the clock signal.The proposed circuit has a simpler construction with respect to previously reported ternary flip-flop.This simple flip-flop with dual-rail outputs uses only twenty-four MOS transistors in addition to the clock driver

and hence requires a small silicon area.The computer simulation with PSPICE has validated that this flip-flop can realize the expected logic function

has desirable transient characteristics and lower power dissipation.Furthermore

the proposed construction can be easily extended to the design of multiple-valued edge-triggered flip-flop with a higher radix.