Design of Low Power Combinational Circuits Based on Redundancy-Restraining Technique

WU Xun-wei; LU Yang-jian; Massoud Medram

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Design of Low Power Combinational Circuits Based on Redundancy-Restraining Technique

更新时间：2025-07-16

- Design of Low Power Combinational Circuits Based on Redundancy-Restraining Technique
- Acta Electronica Sinica Vol. 30, Issue 5, Pages: 672-675(2002)
- 作者机构：
  
  1. 宁波大学电路与系统研究所,浙江,宁波,315211
  2. 浙江大学信电系,浙江,杭州,310027
  3. 美国南加州大学电气工程与系统系,美国 CA,90089
  4. 宁波大学电路与系统研究所浙江宁波,315211
  5. 浙江大学信电系浙江杭州,310027
  6. 美国南加州大学电气工程与系统系美国 CA,90089
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP331TN431
- Published：2002
- 稿件说明：
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WU Xun-wei, LU Yang-jian, Massoud Medram. Design of Low Power Combinational Circuits Based on Redundancy-Restraining Technique[J]. Acta Electronica Sinica, 2002, 30(5): 672-675.
DOI：

WU Xun-wei, LU Yang-jian, Massoud Medram. Design of Low Power Combinational Circuits Based on Redundancy-Restraining Technique[J]. Acta Electronica Sinica, 2002, 30(5): 672-675. DOI：

摘要

本文阐明了基于冗余抑制技术的低功耗电路的设计原理

分析了在组合电路中冗余行为的各种抑制结构及工作机理.作为设计实例

本文提出了基于冗余抑制技术的低功耗比较器设计.PSPICE模拟与能耗分析证明该一设计技术能有效地达到节省功耗的目的.

Abstract

The low power design principle based on redundancy-restraining technique is explained in this paper.Various constructions for restraining redundancy in combinational circuits and their working mechanism are analyzed.Furthermore

a low power magnitude comparator design based on this technique is proposed.PSPICE simulation and energy analysis proves that saving energy dissipation can be effectively achieved by using this design technique.

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