A Small Area Low Power Consumption Mask ROM ASIC Design

CUI Wei; HAN Yue-qiu; CHEN He; LI Yun

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A Small Area Low Power Consumption Mask ROM ASIC Design

更新时间：2025-07-16

- A Small Area Low Power Consumption Mask ROM ASIC Design
- Acta Electronica Sinica Vol. 30, Issue 6, Pages: 934-936(2002)
- 作者机构：
  
  北京理工大学电子工程系,北京,100081
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP333
- Published：2002
- 稿件说明：
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CUI Wei, HAN Yue-qiu, CHEN He, et al. A Small Area Low Power Consumption Mask ROM ASIC Design[J]. Acta Electronica Sinica, 2002, 30(6): 934-936.
DOI：

CUI Wei, HAN Yue-qiu, CHEN He, et al. A Small Area Low Power Consumption Mask ROM ASIC Design[J]. Acta Electronica Sinica, 2002, 30(6): 934-936. DOI：

摘要

本文介绍了一种利用0.6μm单硅双铝双阱CMOS工艺实现的4Kbit掩膜ROM专用集成电路设计(ASIC).ROM单元应用串行结构

整个芯片的面积为0.082mm

.在5伏电源下

功率延迟积为0.036PJ/bit

最大工作电流为1.2mA

最大静态漏电流为0.1μA.采用一种新颖的灵敏放大器有效地提高了ROM的访问速度

ROM的访问时间为36ns.

Abstract

The ASIC design of a 4K bit mask-programmable CMOS ROM is introduced

and the ROM has a small area of 0.082mm

with a power-delay product of 0.036PJ/bit.The high packing density and the excellent power-delay product have been achieved by using double well

single polysilicon

double metal 0.6μm CMOS technology and a serial ROM cell structure.The power supply currents in active and quiescent modes are 1.2mA and less than 0.1μA at +5V

respectively.Using a novel and simple sensitive amplifier/driver structure efficiently reduces the memory access time.The memory access time is 36ns.

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