The paper gives a 2-DCT/IDCT architecture implemented by 1-DCT core according to the characteristic of MPEC-2 video encoder.The architecture's transform matrix is implemented by SRAM which has dual ports for input/output. It has the advantage of high data throughput rate and low chip area. The 1-DCT core is compared with seven multipliers which could be designed according to the computing speed.The paper gives a data arrangement scheme in order to avoid storage confusion of dual ports. What's more

a novel multiplier architecture is given by modifying constant precision which can reduce the hardware cost efficiently. The architecture is validated by FPGA which proves its engineering value.