Configurable Multiplexer CMOS IC Based on Fiber Communication

ZHAO Wen-hu; WANG Zhi-gong; WU Wei; ZHU En

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Configurable Multiplexer CMOS IC Based on Fiber Communication

更新时间：2025-07-16

- Configurable Multiplexer CMOS IC Based on Fiber Communication
- Acta Electronica Sinica Vol. 31, Issue 8, Pages: 1197-1200(2003)
- 作者机构：
  
  东南大学射频与光电集成电路研究所,江苏,南京,210096
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN929
- Published：2003
- 稿件说明：
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ZHAO Wen-hu, WANG Zhi-gong, WU Wei, et al. Configurable Multiplexer CMOS IC Based on Fiber Communication[J]. Acta Electronica Sinica, 2003, 31(8): 1197-1200.
DOI：

ZHAO Wen-hu, WANG Zhi-gong, WU Wei, et al. Configurable Multiplexer CMOS IC Based on Fiber Communication[J]. Acta Electronica Sinica, 2003, 31(8): 1197-1200. DOI：

摘要

本文提出了一种可编程复接方法和结构

通过对编程端的设置可得到2∶1、3∶1、4∶1及5∶1的复接模式.该方法鲁棒性强、应用范围广

其组合可实现除包含大于6的质数之外所有路数的复接

解决了光纤通信系统中不同复接模式对应不同复接结构的问题.通过理论推导

本文着重分析了器件延时和时钟相位对芯片工作的影响

并指出了解决途径.基于本方法和结构的全定制单片集成电路采用0.35μm CMOS工艺制造

芯片面积为24.19mm

实现了串行输出最高数据速率为1.62Gbps的10∶1复接.在1.25Gbps标准速率

工作电压3.3V

负载为50Ω的条件下

功耗仅为174.84mW

输出电压峰-峰值可达到2.42V

占空比为49%

抖动为35ps rms.测试结果表明芯片在复接性能、速度、功耗和面积优化方面的先进性

可满足不同吉比特率通信系统的要求

具有广泛应用和产业化前景.

Abstract

A robust configurable multiplexing approach is proposed

which presented 2∶1

3∶1

4∶1

5∶1 multiplex modes.Its cascade structure can realize all multiplexing modes except prime numbers of greater than 6.Based on this approach

an IC was designed to achieve the 10:1 multiplexing at the bit rate of 1.25Gbps.It used high speed units to improve the design efficiency and to realize low power.It has been developed using 0.35μm CMOS technology and the layout was finished in full custom method.The chip was realized through a foundry technology and measured on wafer.The chip area is 24.19 mm

.The power dissipation is 174.84mW under a 3.3V supply.The measured output voltage is 2.42V

p-p

based on 50Ω load

the d

uty cycle is 49% and the phase jitter is 35ps rms at the 1.25Gbps standard bit rate.The highest speed of serial data is 1.62Gbps.

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